[PATCH v2] RISC-V: Don't trust V from the riscv,isa DT property on T-Head CPUs

[Conor Dooley]

On Wed, Jul 12, 2023 at 06:48:02PM +0100, Conor Dooley wrote:
> From: Palmer Dabbelt <palmer at rivosinc.com>
> 
> The last merge window contained both V support and the deprecation of
> the riscv,isa DT property, with the V implementation reading riscv,isa
> to determine the presence of the V extension.  At the time that was the
> only way to do it, but there's a lot of ambiguity around V in ISA
> strings.  In particular, there is a lot of firmware in the wild that
> uses "v" in the riscv,isa DT property to communicate support for the
> 0.7.1 version of the Vector specification implemented by T-Head CPU
> cores.
> 
> Rather than forcing use of the newly added interface that has strict
> meanings for extensions to detect the presence of vector support, as
> that would penalise those who have behaved, only ignore v in riscv,isa
> on CPUs that report T-Head's vendor ID.
> 
> Fixes: dc6667a4e7e3 ("riscv: Extending cpufeature.c to detect V-extension")
> Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
> Co-developed-by: Conor Dooley <conor.dooley at microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>

From speaking to various people on IRC, and Guo Ren's information that
the c908, which supports the standard version of vector, has non-zero
marchid, we may not need this patch for now.
There's no real urgency to prevent a future regression in support since
marchid will differ between the c908 and the existing cores that only
support the v0.7.1 version of vector, so this could be applied at our
leisure IFF an issue does actually crop up. I've marked it as Changes
Requested on patchwork.
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