[PATCH v2] RISC-V: Don't trust V from the riscv,isa DT property on T-Head CPUs

[Rémi Denis-Courmont]

Le torstaina 13. heinäkuuta 2023, 19.36.49 EEST Jisheng Zhang a écrit :
> On Wed, Jul 12, 2023 at 06:48:02PM +0100, Conor Dooley wrote:
> > From: Palmer Dabbelt <palmer at rivosinc.com>
> > 
> > The last merge window contained both V support and the deprecation of
> > the riscv,isa DT property, with the V implementation reading riscv,isa
> > to determine the presence of the V extension.  At the time that was the
> > only way to do it, but there's a lot of ambiguity around V in ISA
> > strings.  In particular, there is a lot of firmware in the wild that
> > uses "v" in the riscv,isa DT property to communicate support for the
> > 0.7.1 version of the Vector specification implemented by T-Head CPU
> > cores.
> 
> Add Guo
> 
> Hi Conor, Palmer,
> 
> FWICT, new T-HEAD's riscv cores such as C908 support standard RVV-1.0,
> this patch looks like a big hammer for T-HEAD. I do understand why
> this patch is provided, but can we mitigate the situation by carefully
> review the DTs?

There are many tricks to detect that RVV is present but noncomformant at run-
time. If the kernel can at least temporarily enable V to make the check, the 
example below works. Converting the user-space console program to a kernel 
function is left as an exercise to the reader:

----8<--------8<--------8<--------8<--------8<--------8<--------8<----
#include <stdio.h>

int main(void)
{
        long vtype;

        __asm__ (
                "vsetvli zero, zero, e8, m1, ta, ma\n"
                "csrr   %1, vtype\n" : "=r" (vtype) : "r" (0xC0));

        if (vtype < 0)
                puts("RVV 0.7.1");
        else
                puts("RVV 1.0+");

        return 0;
}
----8<--------8<--------8<--------8<--------8<--------8<--------8<----

The trick here is that the vector configuration is valid for RVV 1.0, but not 
for RVV 0.7.1 so the sign/illegal bit gets.

-- 
Rémi Denis-Courmont
http://www.remlab.net/