[PATCH v2 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC
Conor Dooley
conor at kernel.org
Tue Apr 18 10:28:00 PDT 2023
Hey Mason,
Just one minor comment in passing..
On Mon, Apr 17, 2023 at 02:39:42PM +0800, Mason Huo wrote:
> Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC.
> It supports up to 4 cpu frequency loads.
>
> Signed-off-by: Mason Huo <mason.huo at starfivetech.com>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 17 ++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++
> 2 files changed, 50 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index cca1c8040801..b25e6d68ce53 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -227,3 +227,20 @@ &uart0 {
> pinctrl-0 = <&uart0_pins>;
> status = "okay";
> };
> +
> +&U74_1 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_2 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_3 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
> +&U74_4 {
> + cpu-supply = <&vdd_cpu>;
> +};
> +
Applying: riscv: dts: starfive: Add cpu scaling for JH7110 SoC
/stuff/linux/.git/rebase-apply/patch:30: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
Cheers,
Conor.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 228 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-riscv/attachments/20230418/479e8c89/attachment.sig>
More information about the linux-riscv
mailing list