[PATCH 02/12] dt-bindings: riscv: Add T-HEAD C906 and C910 compatibles

[Icenowy Zheng]

在 2022-08-15星期一的 00:08 -0500，Samuel Holland写道：
> The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
> Notably, the C906 core is used in the Allwinner D1 SoC.

Could this get applied first?

C906 and C910 now have a fixed-configuration open-source version, which
means these cores could be played by anyone, and having them in the DT
binding really helps people. In addition I am aware of some C906-
equipped SoC out of Allwinner.

> 
> Signed-off-by: Samuel Holland <samuel at sholland.org>
> ---
> 
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml
> b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 873dd12f6e89..ce2161d9115a 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -38,6 +38,8 @@ properties:
>                - sifive,u5
>                - sifive,u7
>                - canaan,k210
> +              - thead,c906
> +              - thead,c910
>            - const: riscv
>        - items:
>            - enum: