[PATCH v2 0/4] RISC-V: Dynamic ftrace support for RV32I

[patchwork-bot+linux-riscv at kernel.org]

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer at rivosinc.com>:

On Tue, 15 Nov 2022 20:08:28 +0000 you wrote:
> This series enables dynamic ftrace support for RV32I bringing it to
> parity with RV64I.  Most of the work is already there, this is largely
> just assembly fixes to handle register sizes, correct handling of the
> psABI calling convention and Kconfig change.
> 
> Validated with all ftrace boot time self test with qemu for RV32I and
> RV64I in addition to real tracing on an RV32I FPGA design.
> 
> [...]

Here is the summary with links:
  - [v2,1/4] RISC-V: use REG_S/REG_L for mcount
    https://git.kernel.org/riscv/c/8a6841c439df
  - [v2,2/4] RISC-V: reduce mcount save space on RV32
    https://git.kernel.org/riscv/c/3bd7743f8d6d
  - [v2,3/4] RISC-V: preserve a1 in mcount
    https://git.kernel.org/riscv/c/dc58a24db8c1
  - [v2,4/4] RISC-V: enable dynamic ftrace for RV32I
    https://git.kernel.org/riscv/c/f32b4b467ebd

You are awesome, thank you!
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