[PATCH] nvme-pci: set some AMD PCIe downstream storage device to D3 for s2idle

[Christoph Hellwig]

On Tue, May 25, 2021 at 12:11:25PM +0000, Liang, Prike wrote:
> @@ -2856,8 +2856,15 @@ static bool nvme_acpi_storage_d3(struct pci_dev *dev)
>         status = acpi_get_handle(adev->handle, "PXSX", &handle);
>         if (ACPI_FAILURE(status)) {
>                 status = acpi_get_handle(adev->handle, "PEGP", &handle);
> -               if (ACPI_FAILURE(status))
> -                       return false;
> +               if (ACPI_FAILURE(status)) {
> +                       /*
> +                        * In order to support NVMe D3 during s2idle, the property of AMD platform
> +                        * is defined in the GPP6.NVME device.
> +                        */
> +                       status = acpi_get_handle(adev->handle, "\\_SB.PCI0.GPP6.NVME", &handle);
> +                       if (ACPI_FAILURE(status))
> +                               return false;
> +               }

This whole chink also really needs to move out of the NVMe driver.  We
can't accumulate tons of crap in a generic PCIe driver to work around
all kinds of broken x86 platforms.