[PATCH] nvme-pci: set some AMD PCIe downstream storage device to D3 for s2idle

[Liang, Prike]

[Public]

> -----Original Message-----
> From: Christoph Hellwig <hch at lst.de>
> Sent: Tuesday, May 25, 2021 2:21 PM
> To: Liang, Prike <Prike.Liang at amd.com>
> Cc: kbusch at kernel.org; axboe at fb.com; hch at lst.de; sagi at grimberg.me;
> linux-nvme at lists.infradead.org; Deucher, Alexander
> <Alexander.Deucher at amd.com>; S-k, Shyam-sundar <Shyam-sundar.S-
> k at amd.com>; Limonciello, Mario <Mario.Limonciello at amd.com>
> Subject: Re: [PATCH] nvme-pci: set some AMD PCIe downstream storage
> device to D3 for s2idle
>
> On Tue, May 25, 2021 at 10:48:59AM +0800, Prike Liang wrote:
> > +#ifdef CONFIG_X86
> > +#include <asm/cpu_device_id.h>
> > +#endif
> >
> >  #include "trace.h"
> >  #include "nvme.h"
> > @@ -2828,6 +2831,16 @@ static unsigned long
> > check_vendor_combination_bug(struct pci_dev *pdev)  }
> >
> >  #ifdef CONFIG_ACPI
> > +
> > +#ifdef CONFIG_X86
> > +static const struct x86_cpu_id storage_d3_cpu_ids[] = {
> > +   X86_MATCH_VENDOR_FAM_MODEL(AMD, 25, 80, NULL),
> /*Cezanne*/
> > +   X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 96, NULL), /*Renoir*/
> > +   X86_MATCH_VENDOR_FAM_MODEL(AMD, 23, 104,
> NULL),/*Lucienne*/
> > +   {}
> > +};
> > +#endif
>
> This is completely unacceptable.  The NVMe driver could not care less what
> CPU we on.  We need information from the PCI or power managment core
> on how broken the power management of the root port is, not this kind of
> crap in a low-level driver, with potentially many more needing the same kind
> of quirk in the future.
This solution NAK is reasonable from software decouple perspective. As to this issue
seems only take care the NVMe D3 support during s2idle and the StorageD3Enable property
is defined for this purpose. How about approach this issue directly like as following fix?

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 6bad4d4..8d89c84 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2856,8 +2856,15 @@ static bool nvme_acpi_storage_d3(struct pci_dev *dev)
        status = acpi_get_handle(adev->handle, "PXSX", &handle);
        if (ACPI_FAILURE(status)) {
                status = acpi_get_handle(adev->handle, "PEGP", &handle);
-               if (ACPI_FAILURE(status))
-                       return false;
+               if (ACPI_FAILURE(status)) {
+                       /*
+                        * In order to support NVMe D3 during s2idle, the property of AMD platform
+                        * is defined in the GPP6.NVME device.
+                        */
+                       status = acpi_get_handle(adev->handle, "\\_SB.PCI0.GPP6.NVME", &handle);
+                       if (ACPI_FAILURE(status))
+                               return false;
+               }
        }