[PATCH v3 3/5] spi: spi-mem: Allow specifying the byte order in DTR mode

[Michael Walle]

Hi,

>> > There are NOR flashes (Macronix) that swap the bytes on a 16-bit
>> > boundary when configured in Octal DTR mode. The byte order of
>> > 16-bit words is swapped when read or written in Octal Double
>> > Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
>> > modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses
>> > 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2.
>> > Swapping the bytes may introduce some endianness problems. It can
>> > affect the boot sequence if the entire boot sequence is not handled
>> > in either 8D-8D-8D mode or 1-1-1 mode. So we must swap the bytes
>> > back to have the same byte order as in STR modes. Fortunately there
>> > are controllers that could swap the bytes back at runtime,
>> > addressing the flash's endiannesses requirements. Provide a way for
>> > the upper layers to specify the byte order in Octal DTR mode.
>> >
>> > Signed-off-by: Tudor Ambarus <tudor.ambarus at linaro.org>
>> 
>> .. this. If you pick up a patch from another author, you should
>> keep the author of the patch.
> How could I do for this?
> Because of Tudor's patch is on old Linux kernel version, it need
> a small changes for suiting on v6.5-rc3.

Ahh I see, you changed that patch. I'd pick up the patch, leave the
original author and SoB, describe your changes and add your SoB
after the one from Tudor.

But I still don't see how these patches will help with your current
problem.

-michael