[PATCH v3 3/5] spi: spi-mem: Allow specifying the byte order in DTR mode

[liao jaime]

Hi Michael

>
> Am 2023-08-04 11:54, schrieb Jaime Liao:
> > From: JaimeLiao <jaimeliao at mxic.com.tw>
>
> This doesn't match..
>
> >
> > There are NOR flashes (Macronix) that swap the bytes on a 16-bit
> > boundary when configured in Octal DTR mode. The byte order of
> > 16-bit words is swapped when read or written in Octal Double
> > Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
> > modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses
> > 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2.
> > Swapping the bytes may introduce some endianness problems. It can
> > affect the boot sequence if the entire boot sequence is not handled
> > in either 8D-8D-8D mode or 1-1-1 mode. So we must swap the bytes
> > back to have the same byte order as in STR modes. Fortunately there
> > are controllers that could swap the bytes back at runtime,
> > addressing the flash's endiannesses requirements. Provide a way for
> > the upper layers to specify the byte order in Octal DTR mode.
> >
> > Signed-off-by: Tudor Ambarus <tudor.ambarus at linaro.org>
>
> .. this. If you pick up a patch from another author, you should
> keep the author of the patch.
How could I do for this?
Because of Tudor's patch is on old Linux kernel version, it need
a small changes for suiting on v6.5-rc3.

>
> -michael
>
> > ---
> >  drivers/spi/spi-mem.c       | 3 +++
> >  include/linux/spi/spi-mem.h | 6 ++++++
> >  2 files changed, 9 insertions(+)
> >
> > diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
> > index edd7430d4c05..fd6b1c69ab9b 100644
> > --- a/drivers/spi/spi-mem.c
> > +++ b/drivers/spi/spi-mem.c
> > @@ -171,6 +171,9 @@ bool spi_mem_default_supports_op(struct spi_mem
> > *mem,
> >       if (op_is_dtr) {
> >               if (!spi_mem_controller_is_capable(ctlr, dtr))
> >                       return false;
> > +             if (op->data.dtr_swab16 &&
> > +                 !(spi_mem_controller_is_capable(ctlr, dtr_swab16)))
> > +                     return false;
> >
> >               if (op->cmd.nbytes != 2)
> >                       return false;
> > diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
> > index 8e984d75f5b6..9da6d53a29a3 100644
> > --- a/include/linux/spi/spi-mem.h
> > +++ b/include/linux/spi/spi-mem.h
> > @@ -89,6 +89,8 @@ enum spi_mem_data_dir {
> >   * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or
> > not
> >   * @data.buswidth: number of IO lanes used to send/receive the data
> >   * @data.dtr: whether the data should be sent in DTR mode or not
> > + * @data.dtr_swab16: whether the byte order of 16-bit words is swapped
> > when read
> > + *                or written in Octal DTR mode compare to STR mode
> >   * @data.ecc: whether error correction is required or not
> >   * @data.dir: direction of the transfer
> >   * @data.nbytes: number of data bytes to send/receive. Can be zero if
> > the
> > @@ -120,6 +122,7 @@ struct spi_mem_op {
> >       struct {
> >               u8 buswidth;
> >               u8 dtr : 1;
> > +             u8 dtr_swab16 : 1;
> >               u8 ecc : 1;
> >               enum spi_mem_data_dir dir;
> >               unsigned int nbytes;
> > @@ -290,10 +293,13 @@ struct spi_controller_mem_ops {
> >  /**
> >   * struct spi_controller_mem_caps - SPI memory controller capabilities
> >   * @dtr: Supports DTR operations
> > + * @dtr_swab16: Supports swapping bytes on a 16 bit boundary when
> > configured in
> > +             Octal DTR
> >   * @ecc: Supports operations with error correction
> >   */
> >  struct spi_controller_mem_caps {
> >       bool dtr;
> > +     bool dtr_swab16;
> >       bool ecc;
> >  };

Thanks your review
Jaime