[PATCH 2/2] mtd: spi-nor: Support SPI_NOR_DUAL_READ on Micron mt25qu02g.

[Tudor.Ambarus at microchip.com]

Hi, David,

On 7/17/20 9:00 PM, David Clear wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Fri, Jul 17, 2020 at 3:33 AM <Tudor.Ambarus at microchip.com> wrote:
>> On 7/17/20 12:16 AM, David Clear wrote:
>>> The Micron mt25qu02g supports both x2 and x4 transactions.  Add the
>>> SPI_NOR_DUAL_READ to its spi_nor_ids[] table entry.
>>
>> In spi_nor_select_read() we select the fastest read. Since this flash
>> supports Quad Read, the Dual Read will never get selected. As of now,
>> there is no benefit in adding SPI_NOR_DUAL_READ when SPI_NOR_QUAD_READ
>> is specified.
> 
> Ok, I've got this now:  I went back and did some more testing with different
> spi-rx-bus-width properties and I see it's redundant to specify both DUAL and
> QUAD in the flash description.  Thanks for pointing out my error. I learned
> something new.
> 
> I withdraw this patch and will work on getting the Macronix patch cleaned up and
> tests documented.

No, please keep this patch as well. You were right. If we remove the
SPI_NOR_DUAL_READ flag, the dual read will work only because the SPI_NOR_QUAD_READ
flag triggers the parsing of SFDP, which will fill the dual read caps. It is
better to statically fill the 1-1-2 read, so that we can still use the dual read
if SFDP parsing fails and will not fill the dual read caps. Let's keep it.

Thanks, David.
ta