Fwd: [PATCH 2/2] mtd: spi-nor: Support SPI_NOR_DUAL_READ on Micron mt25qu02g.

[David Clear]

[resend due to mailing list bounce]
On Fri, Jul 17, 2020 at 3:33 AM <Tudor.Ambarus at microchip.com> wrote:
>
> > The Micron mt25qu02g supports both x2 and x4 transactions.  Add the
> > SPI_NOR_DUAL_READ to its spi_nor_ids[] table entry.
>
> In spi_nor_select_read() we select the fastest read. Since this flash
> supports Quad Read, the Dual Read will never get selected. As of now,
> there is no benefit in adding SPI_NOR_DUAL_READ when SPI_NOR_QUAD_READ
> is specified.

We're using these devices with the drivers/spi/spi-cadence-quadspi.c
controller.  Now that the Cadence driver is in the spi subsystem, the
spi-rx-bus-width property in the device-tree is honored, and the fastest
available read is selected, taking the bus-width into account.

Only two data pins are hooked up on our board, so we need the x2
mode to work.

> &qspi {
>         status = "okay";
>         flash0: flash at 0 {
>                 compatible = "jedec,spi-nor";
>                 reg = <0>;
>                 spi-max-frequency = <50000000>;
>                 spi-rx-bus-width = <2>;

Without this property the interface runs in x1 mode.  Both <2> and
<4> appropriately take effect on this controller (x4 verified under
simulation).

Regards,
David.