[PATCH v2 2/5] clk: sunxi-ng: mp: support clocks with just a shift register

[Andre Przywara]

On Fri, 18 Sep 2026 11:51:19 +0800
Chen-Yu Tsai <wens at kernel.org> wrote:

Hi,

> On Fri, Sep 18, 2026 at 6:39 AM Andre Przywara <andre.przywara at arm.com> wrote:
> >
> > The "mp" clock models a mod clock with divider and a shift field. At
> > least one clock in the Allwinner A523 features just a power-of-2 divider
> > field, so support an initialisation of the clock without providing an
> > actual divider field.
> 
> Please just use the single divider clock type instead. It properly supports
> power-of-2 dividers.

Ah, indeed, there is SUNXI_CCU_P_DATA_WITH_MUX_GATE now, will drop this
patch then.

So when using that macro it looks like this:
static SUNXI_CCU_P_DATA_WITH_MUX_GATE(pll_cpu_l_div_clk, "pll-cpu-l-div",
                                      pll_cpu_l_hws, 0x060,
                                      16, 2,                    /* P */
                                      0, 0,                     /* no mux */
                                      0,                        /* no gate */
                                      CLK_SET_RATE_PARENT);     /* flags */

There are still some unused bits, does that look OK or shall I add a
macro that allows to skip mux and gate?
static SUNXI_CCU_P_DATA(pll_cpu_l_div_clk, "pll-cpu-l-div",
			pll_cpu_l_hws, 0x60,
			16, 2,			/* P */
			CLK_SET_RATE_PARENT);	/* flags */

Cheers,
Andre


> 
> ChenYu
> 
> > Add a check whether the "width" field is 0, and skip the divider
> > handling in this case, as the GENMASK macro will not work with a zero
> > length.
> >
> > Signed-off-by: Andre Przywara <andre.przywara at arm.com>
> > ---
> >  drivers/clk/sunxi-ng/ccu_mp.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
> > index 7cdb0eedc69b5..3896cb94bf733 100644
> > --- a/drivers/clk/sunxi-ng/ccu_mp.c
> > +++ b/drivers/clk/sunxi-ng/ccu_mp.c
> > @@ -236,9 +236,11 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
> >         spin_lock_irqsave(cmp->common.lock, flags);
> >
> >         reg = readl(cmp->common.base + cmp->common.reg);
> > -       reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
> > +       if (cmp->m.width)
> > +               reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
> >         reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
> > -       reg |= (m - cmp->m.offset) << cmp->m.shift;
> > +       if (cmp->m.width)
> > +               reg |= (m - cmp->m.offset) << cmp->m.shift;
> >         if (shift)
> >                 reg |= ilog2(p) << cmp->p.shift;
> >         else
> > --
> > 2.43.0
> >
>