[PATCH] RISC-V: Skip stopping cycle counter

[Andrew Jones]

On Mon, Feb 02, 2026 at 07:17:28PM +0800, qingwei.hu wrote:
> From: Qingwei Hu <qingwei.hu at bytedance.com>
> 
> In the riscv_pmu_sbi driver, pmu_sbi_stop_all() is intended to stop
> all available counters. However, counter 0 (the cycle counter) should
> be excluded from this operation because the counter may be used in
> user mode by rdcycle.

Hi Qingwei,

It looks like Chen Pei beat you to this[1], but that patch also avoids
stopping TIME and INSTRET.

[1] https://lore.kernel.org/all/20260131112440.2915-1-cp0613@linux.alibaba.com/

Thanks,
drew

> 
> Signed-off-by: Qingwei Hu <qingwei.hu at bytedance.com>
> ---
>  drivers/perf/riscv_pmu_sbi.c | 10 +++++++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 7dd282da67ce..2bc0050dabd2 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -900,11 +900,15 @@ static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask)
>  static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
>  {
>  	/*
> -	 * No need to check the error because we are disabling all the counters
> -	 * which may include counters that are not enabled yet.
> +	 * No need to check the error because we are disabling all available
> +	 * counters (except the cycle counter) which may include counters
> +	 * that are not enabled yet.
> +	 *
> +	 * Cycle counter is excluded because it might be accessed by user
> +	 * mode via rdcycle.
>  	 */
>  	sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP,
> -		  0, pmu->cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0);
> +		  0, pmu->cmask & ~BIT(0), SBI_PMU_STOP_FLAG_RESET, 0, 0, 0);
>  }
>  
>  static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu)
> -- 
> 2.39.5
> 
> 
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