[PATCH v4 5/7] arm64: Add support for FEAT_{LS64, LS64_V}

[Catalin Marinas]

On Mon, Sep 15, 2025 at 04:29:25PM +0800, Yicong Yang wrote:
> On 2025/9/12 21:47, Jonathan Cameron wrote:
> > On Thu, 11 Sep 2025 16:50:14 +0100
> > Will Deacon <will at kernel.org> wrote:
> >> On Tue, Sep 09, 2025 at 09:48:04AM +0800, Yicong Yang wrote:
> >>> per ARM DDI0487 L.b section C3.2.6,
> >>>
> >>>   When the instructions access a memory type that is not one of the following,
> >>>   a data abort for unsupported Exclusive or atomic access is generated...  
> >>
> >> That's about the memory _type_. I'm talking about a supported memory type
> >> (e.g. writeback cacheable) but when the physical location doesn't support
> >> the instruction. That's captured a little later in the same section:
> >>
> >>   | If the target memory location does not support the LD64B or ST64B
> >>   | instructions, then one of the following behaviors occurs:
> >>   |  * A stage 1 Data Abort, reported using the DFSC code of 0b110101,
> >>   |    is generated.
> >>   |  * The instruction performs the memory accesses, but the accesses
> >>   |    are not single-copy atomic above the byte level

Is this a new addition to the L.b release of the ARM ARM? Maybe it was
there before in some other form (or a different place). At least it
doesn't say "unpredictable".

> >> and I think that's a bad interface to expose blindly to userspace solely
> >> as a boolean hwcap.
> > 
> > Nasty, so now I'm curious. Any thoughts on how to expose what regions it is appropriate
> > for?  I can think of various heavy weight options but wondering if there is a simple
> > solution.
> 
> in my understanding the hwcap only describes the capabilities of the CPU but not
> the whole system. the users should make sure the function works as expected if the
> CPU supports it and they're going to use it. specifically the LS64 is intended for
> device memory only, so the user should take responsibility of using it on supported
> memory.

We have other cases like MTE where we avoid exposing the HWCAP to user
if we know the memory system does not support MTE, though we intercepted
this early and asked the (micro)architects to tie the CPU ID field to
what the system supports.

> may raise the similar question if use other atomic instructions (e.g. LSE) on the
> memory does not support atomicity. find this restriction in ARM DDI0487 L.b section B2.2.6
> 
>   Some system implementations might not support atomic instructions for all regions of the
>   memory

With exclusives or atomics, we require that the general purpose (system)
RAM supports the feature, otherwise Linux won't work properly (I don't
think we specifically documented this but it would be fairly obvious
when the kernel doesn't boot or user-space randomly crashes).

> and if perform atomic instruction on unsupported memory it's allowed to implement as
> 
>   * The instruction generates a synchronous External abort.
>   * The instruction generates a System Error interrupt.
>   * The instruction generates an IMPLEMENTATION DEFINED MMU fault reported using the Data
>     Abort Fault status code of ESR_ELx.DFSC = 110101.
>   * The instruction is treated as a NOP.
>   * The instructions are performed, but there is no guarantee that the memory accesses were
>     performed atomically in regard to other agents that access memory. In this case, the
>     instruction might also generate a System Error interrupt.
> 
> if instruction performed without generate a SEI in the last implementation, it's quite similar
> to the condition of LS64.

The difference is that we don't support Linux on such systems.

Arguably, the use of LD/ST64B* is fairly specialised and won't be used
on the general purpose RAM and by random applications. It needs a device
driver to create the NC/Device mapping and specific programs/libraries
to access it. I'm not sure the LS64 properties are guaranteed by the
device alone or the device together with the interconnect. I suspect the
latter and neither the kernel driver nor user space can tell. In the
best case, you get a fault and realise the system doesn't work as
expected. Worse is the non-atomicity with potentially silent corruption.

So, to Will's point, the HWCAP is not sufficient for user space to make
an informed decision on whether it can safely use the LS64 instructions.
Can a (generic) device driver tell or do we need additional information
in firmware tables to advertise the correct behaviour?

-- 
Catalin