[PATCH v4 5/7] arm64: Add support for FEAT_{LS64, LS64_V}

[Yicong Yang]

On 2025/9/12 21:47, Jonathan Cameron wrote:
> On Thu, 11 Sep 2025 16:50:14 +0100
> Will Deacon <will at kernel.org> wrote:
> 
>> On Tue, Sep 09, 2025 at 09:48:04AM +0800, Yicong Yang wrote:
>>> On 2025/9/8 20:01, Will Deacon wrote:  
>>>> On Tue, Jul 15, 2025 at 04:13:54PM +0800, Yicong Yang wrote:  
>>>>> diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst
>>>>> index 69d7afe56853..9e6db258ff48 100644
>>>>> --- a/Documentation/arch/arm64/elf_hwcaps.rst
>>>>> +++ b/Documentation/arch/arm64/elf_hwcaps.rst
>>>>> @@ -435,6 +435,12 @@ HWCAP2_SME_SF8DP4
>>>>>  HWCAP2_POE
>>>>>      Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001.
>>>>>  
>>>>> +HWCAP3_LS64
>>>>> +    Functionality implied by ID_AA64ISAR1_EL1.LS64 == 0b0001.
>>>>> +
>>>>> +HWCAP3_LS64_V
>>>>> +    Functionality implied by ID_AA64ISAR1_EL1.LS64 == 0b0010.  
>>>>
>>>> Given that these instructions only work on IMPLEMENTATION DEFINED memory
>>>> locations and aren't guaranteed to generate an abort if used elsewhere,
>>>> how is userspace supposed to know what to do with them?
>>>>   
>>>
>>> per ARM DDI0487 L.b section C3.2.6,
>>>
>>>   When the instructions access a memory type that is not one of the following,
>>>   a data abort for unsupported Exclusive or atomic access is generated...  
>>
>> That's about the memory _type_. I'm talking about a supported memory type
>> (e.g. writeback cacheable) but when the physical location doesn't support
>> the instruction. That's captured a little later in the same section:
>>
>>   | If the target memory location does not support the LD64B or ST64B
>>   | instructions, then one of the following behaviors occurs:
>>   |  * A stage 1 Data Abort, reported using the DFSC code of 0b110101,
>>   |    is generated.
>>   |  * The instruction performs the memory accesses, but the accesses
>>   |    are not single-copy atomic above the byte level
>>
>> and I think that's a bad interface to expose blindly to userspace solely
>> as a boolean hwcap.
> Hi Will,
> 
> Nasty, so now I'm curious. Any thoughts on how to expose what regions it is appropriate
> for?  I can think of various heavy weight options but wondering if there is a simple
> solution.
> 

in my understanding the hwcap only describes the capabilities of the CPU but not
the whole system. the users should make sure the function works as expected if the
CPU supports it and they're going to use it. specifically the LS64 is intended for
device memory only, so the user should take responsibility of using it on supported
memory.

may raise the similar question if use other atomic instructions (e.g. LSE) on the
memory does not support atomicity. find this restriction in ARM DDI0487 L.b section B2.2.6

  Some system implementations might not support atomic instructions for all regions of the
  memory

and if perform atomic instruction on unsupported memory it's allowed to implement as

  * The instruction generates a synchronous External abort.
  * The instruction generates a System Error interrupt.
  * The instruction generates an IMPLEMENTATION DEFINED MMU fault reported using the Data
    Abort Fault status code of ESR_ELx.DFSC = 110101.
  * The instruction is treated as a NOP.
  * The instructions are performed, but there is no guarantee that the memory accesses were
    performed atomically in regard to other agents that access memory. In this case, the
    instruction might also generate a System Error interrupt.

if instruction performed without generate a SEI in the last implementation, it's quite similar
to the condition of LS64.

thanks.