[PATCH v2 9/9] arm64: dts: imx95: Describe Mali G310 GPU

Marek Vasut marek.vasut at mailbox.org
Thu Sep 4 06:22:18 PDT 2025


On 9/4/25 11:54 AM, Peng Fan wrote:

Hello Peng,

>>> @@ -1890,6 +1919,35 @@ netc_emdio: mdio at 0,0 {
>>>   			};
>>>   		};
>>>   
>>> +		gpu_blk_ctrl: reset-controller at 4d810000 {
>>> +			compatible = "nxp,imx95-gpu-blk-ctrl";
>>> +			reg = <0x0 0x4d810000 0x0 0xc>;
>>> +			#reset-cells = <1>;
>>> +			clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
>>> +			assigned-clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
>>> +			assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
>>> +			assigned-clock-rates = <133333333>;
>>> +			power-domains = <&scmi_devpd IMX95_PD_GPU>;
>>> +		};
>>
>> With the SM release lf-6.12.3-1.0.0 AP does not have any access to
>> this BLK_CTRL anymore. See [1]
> 
> Right. In configs/mx95evk.cfg, BLK_CTRL_GPUMIX is assigned to M33P, and
> System manager will automatically handle this reset.
This discussion will get interesting, because there are systems in the 
field where this is not the case, and they cannot easily update their 
bootloader. How do we handle that ?

I can still update most of the systems I care about, but this really 
isn't the way to handle this, because this reset part is part of 
firmware ABI, which has changed now.



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