[PATCH v2 9/9] arm64: dts: imx95: Describe Mali G310 GPU

[Peng Fan]

On Mon, Mar 24, 2025 at 08:02:06AM +0100, Alexander Stein wrote:
>Am Freitag, 21. M?rz 2025, 21:05:59 CET schrieb Marek Vasut:
>> The instance of the GPU populated in i.MX95 is the G310,
>> describe this GPU in the DT. Include description of the
>> GPUMIX block controller, which can be operated as a simple
>> reset. Include dummy GPU voltage regulator and OPP tables.
>> 
>> Signed-off-by: Marek Vasut <marex at denx.de>
>> ---
>> Cc: Boris Brezillon <boris.brezillon at collabora.com>
>> Cc: Conor Dooley <conor+dt at kernel.org>
>> Cc: David Airlie <airlied at gmail.com>
>> Cc: Fabio Estevam <festevam at gmail.com>
>> Cc: Krzysztof Kozlowski <krzk+dt at kernel.org>
>> Cc: Liviu Dudau <liviu.dudau at arm.com>
>> Cc: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
>> Cc: Maxime Ripard <mripard at kernel.org>
>> Cc: Pengutronix Kernel Team <kernel at pengutronix.de>
>> Cc: Philipp Zabel <p.zabel at pengutronix.de>
>> Cc: Rob Herring <robh at kernel.org>
>> Cc: Sascha Hauer <s.hauer at pengutronix.de>
>> Cc: Sebastian Reichel <sre at kernel.org>
>> Cc: Shawn Guo <shawnguo at kernel.org>
>> Cc: Simona Vetter <simona at ffwll.ch>
>> Cc: Steven Price <steven.price at arm.com>
>> Cc: Thomas Zimmermann <tzimmermann at suse.de>
>> Cc: devicetree at vger.kernel.org
>> Cc: dri-devel at lists.freedesktop.org
>> Cc: imx at lists.linux.dev
>> Cc: linux-arm-kernel at lists.infradead.org
>> ---
>> V2: - Drop regulator-{always,boot}-on from fixed-gpu-reg regulator
>>     - Keep the GPU and GPUMIX always enabled
>>     - Switch from fsl, to nxp, vendor prefix
>>     - Fix opp_table to opp-table
>>     - Describe IMX95_CLK_GPUAPB as coregroup clock
>>     - Sort interrupts by their names to match bindings
>> ---
>>  arch/arm64/boot/dts/freescale/imx95.dtsi | 58 ++++++++++++++++++++++++
>>  1 file changed, 58 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
>> index 9bb26b466a061..3acdbd7fd4eee 100644
>> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
>> @@ -249,6 +249,35 @@ dummy: clock-dummy {
>>  		clock-output-names = "dummy";
>>  	};
>>  
>> +	gpu_fixed_reg: fixed-gpu-reg {
>> +		compatible = "regulator-fixed";
>> +		regulator-min-microvolt = <920000>;
>> +		regulator-max-microvolt = <920000>;
>> +		regulator-name = "vdd_gpu";
>> +	};
>> +
>> +	gpu_opp_table: opp-table {
>> +		compatible = "operating-points-v2";
>> +
>> +		opp-500000000 {
>> +			opp-hz = /bits/ 64 <500000000>;
>> +			opp-hz-real = /bits/ 64 <500000000>;
>> +			opp-microvolt = <920000>;
>> +		};
>> +
>> +		opp-800000000 {
>> +			opp-hz = /bits/ 64 <800000000>;
>> +			opp-hz-real = /bits/ 64 <800000000>;
>> +			opp-microvolt = <920000>;
>> +		};
>> +
>> +		opp-1000000000 {
>> +			opp-hz = /bits/ 64 <1000000000>;
>> +			opp-hz-real = /bits/ 64 <1000000000>;
>> +			opp-microvolt = <920000>;
>> +		};
>> +	};
>> +
>>  	clk_ext1: clock-ext1 {
>>  		compatible = "fixed-clock";
>>  		#clock-cells = <0>;
>> @@ -1890,6 +1919,35 @@ netc_emdio: mdio at 0,0 {
>>  			};
>>  		};
>>  
>> +		gpu_blk_ctrl: reset-controller at 4d810000 {
>> +			compatible = "nxp,imx95-gpu-blk-ctrl";
>> +			reg = <0x0 0x4d810000 0x0 0xc>;
>> +			#reset-cells = <1>;
>> +			clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
>> +			assigned-clocks = <&scmi_clk IMX95_CLK_GPUAPB>;
>> +			assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
>> +			assigned-clock-rates = <133333333>;
>> +			power-domains = <&scmi_devpd IMX95_PD_GPU>;
>> +		};
>
>With the SM release lf-6.12.3-1.0.0 AP does not have any access to
>this BLK_CTRL anymore. See [1]

Right. In configs/mx95evk.cfg, BLK_CTRL_GPUMIX is assigned to M33P, and
System manager will automatically handle this reset.

Regards
Peng

>
>Best regards,
>Alexander
>
>[1] https://github.com/nxp-imx/imx-sm/blob/master/sm/doc/rn_cl.md#sm-184-deassert-the-gpu-reset-when-the-gpumix-is-powered-up-rn_detail_sm_184
>
>> +
>> +		gpu: gpu at 4d900000 {
>> +			compatible = "nxp,imx95-mali", "arm,mali-valhall-csf";
>> +			reg = <0 0x4d900000 0 0x480000>;
>> +			clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>;
>> +			clock-names = "core", "coregroup";
>> +			interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "job", "mmu", "gpu";
>> +			mali-supply = <&gpu_fixed_reg>;
>> +			operating-points-v2 = <&gpu_opp_table>;
>> +			power-domains = <&scmi_devpd IMX95_PD_GPU>, <&scmi_perf IMX95_PERF_GPU>;
>> +			power-domain-names = "mix", "perf";
>> +			resets = <&gpu_blk_ctrl 0>;
>> +			#cooling-cells = <2>;
>> +			dynamic-power-coefficient = <1013>;
>> +		};
>> +
>>  		ddr-pmu at 4e090dc0 {
>>  			compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";
>>  			reg = <0x0 0x4e090dc0 0x0 0x200>;
>> 
>
>
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