[PATCH 1/3] perf/imx_ddr: speed up overflow frequency of cycle counter

[Xu Yang]

Hi Frank,

> -----Original Message-----
> From: Frank Li <frank.li at nxp.com>
> Sent: Wednesday, July 5, 2023 10:57 PM
> To: Xu Yang <xu.yang_2 at nxp.com>
> Cc: will at kernel.org; mark.rutland at arm.com; shawnguo at kernel.org; s.hauer at pengutronix.de; kernel at pengutronix.de;
> dl-linux-imx <linux-imx at nxp.com>; linux-arm-kernel at lists.infradead.org
> Subject: RE: [PATCH 1/3] perf/imx_ddr: speed up overflow frequency of cycle counter
> 
> > +
> > +		/*
> > +		 * Workaround for i.MX8MP:
> > +		 * Common counters and byte counters share the same
> > COUNTER_CNTL,
> > +		 * and byte counters could overflow before cycle counter.
> > Need set
> > +		 * counter parameter(CP) of cycle counter to give it initial
> > value
> > +		 * which can speed up cycle counter overflow frequency.
> > +		 */
> > +		if ((pmu->devtype_data->quirks &
> > DDR_CAP_AXI_ID_FILTER_ENHANCED) ==
> > +		    DDR_CAP_AXI_ID_FILTER_ENHANCED) {
> 
> needn't `==`
> if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED)

No, this workaround is only for imx8mp. We need this condition to filter
it.

> 
> Did you fixed cycle counter also? Dose cycle counter read get correct value?

Does cycle counter has some issues? I have tested it and can get correct
value from cycle counter.

Thanks,
Xu Yang

> 
> Frank
> 
> > +			if (counter == EVENT_CYCLES_COUNTER)
> > +				val |= FIELD_PREP(CNTL_CP_MASK, 0xf0);
> > +		}
> > +
> >  		writel(val, pmu->base + reg);
> >  	} else {
> >  		/* Disable counter */
> > --
> > 2.34.1