[PATCH] arm64: dma: Drop cache invalidation from arch_dma_prep_coherent()

[Catalin Marinas]

On Thu, Sep 08, 2022 at 11:32:15AM +0100, Catalin Marinas wrote:
> On Wed, Sep 07, 2022 at 05:25:43PM +0100, Will Deacon wrote:
> > On Wed, Sep 07, 2022 at 10:27:45AM +0100, Robin Murphy wrote:
> > > It seems like we don't stand to gain much by removing the invalidation -
> > > since the overhead will still be in the clean - other than the potential for
> > > a slightly increased chance of rare and hard-to-debug memory corruption :/
> > 
> > I just find it odd that we rely on the CPU not hitting the cacheable alias
> > in other places, yet we're using an invalidation for this path. It's
> > inconsistent and difficult to explain to people. As I said, I'm happy to
> > add a comment to the existing code instead of the change here, but I don't
> > know what to say other than something like:
> > 
> >   /*
> >    * The architecture says we only need a clean here, but invalidate as
> >    * well just in case.
> >    */
[...]
> So yeah, I think a clean is needed here or clean+invalidate but not
> invalidate only due to the addition of MTE.

OK, I think invalidate works as well. The ARM ARM has a note on the DC
IVAC instruction:

  When FEAT_MTE is implemented, this instruction might invalidate
  Allocation Tags from caches. When it invalidates Allocation Tags from
  caches, it also cleans them.

(hopefully it cleans them first before invalidating)

-- 
Catalin