[PATCH] arm64/kvm: extract ESR_ELx.EC only

[Will Deacon]

On Wed, Nov 03, 2021 at 11:05:45AM +0000, Mark Rutland wrote:
> Since ARMv8.0 the upper 32 bits of ESR_ELx have been RES0, and recently
> some of the upper bits gained a meaning and can be non-zero. For
> example, when FEAT_LS64 is implemented, ESR_ELx[36:32] contain ISS2,
> which for an ST64BV or ST64BV0 can be non-zero. This can be seen in ARM
> DDI 0487G.b, page D13-3145, section D13.2.37.
> 
> Generally, we must not rely on RES0 bit remaining zero in future, and
> when extracting ESR_ELx.EC we must mask out all other bits.
> 
> All C code uses the ESR_ELx_EC() macro, which masks out the irrelevant
> bits, and therefore no alterations are required to C code to avoid
> consuming irrelevant bits.
> 
> In a couple of places the KVM assembly extracts ESR_ELx.EC using LSR on
> an X register, and so could in theory consume previously RES0 bits. In
> both cases this is for comparison with EC values ESR_ELx_EC_HVC32 and
> ESR_ELx_EC_HVC64, for which the upper bits of ESR_ELx must currently be
> zero, but this could change in future.
> 
> This patch adjusts the KVM vectors to use UBFX rather than LSR to
> extract ESR_ELx.EC, ensuring these are robust to future additions to
> ESR_ELx.
> 
> Cc: stable at vger.kernel.org
> Signed-off-by: Mark Rutland <mark.rutland at arm.com>
> Cc: Alexandru Elisei <alexandru.elisei at arm.com>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: James Morse <james.morse at arm.com>
> Cc: Marc Zyngier <maz at kernel.org>
> Cc: Suzuki K Poulose <suzuki.poulose at arm.com>
> Cc: Will Deacon <will at kernel.org>
> ---
>  arch/arm64/include/asm/esr.h   | 1 +
>  arch/arm64/kvm/hyp/hyp-entry.S | 2 +-
>  arch/arm64/kvm/hyp/nvhe/host.S | 2 +-
>  3 files changed, 3 insertions(+), 2 deletions(-)

Acked-by: Will Deacon <will at kernel.org>

Will