[PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY

[Tomi Valkeinen]

Hi Nishanth,

On 17/09/2020 16:07, Nishanth Menon wrote:
> On 10:12-20200917, Tomi Valkeinen wrote:
>> Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP
>> 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper.
>>
>> A slight irregularity in the bindings is the DPTX PHY register block,
>> which is in the MHDP IP, but is needed and mapped by the PHY.
>>
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen at ti.com>
> 
> just quick notes below:
> 
>> ---
>>  arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 104 ++++++++++++++++++++++
>>  1 file changed, 104 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index 12ceea9b3c9a..82d89dd3faf5 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -553,6 +553,82 @@ serdes3: serdes at 5030000 {
>>  		};
>>  	};
>>  
>> +	serdes_wiz4: wiz at 5050000 {
> serdes-mux ? - I think we might want to cleanup other similar usage
> instead of "wiz" or maybe just "mux"?
> 
>> +		compatible = "ti,j721e-wiz-10g";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
>> +		clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&dummy_cmn_refclk>;
>> +		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
>> +		assigned-clocks = <&k3_clks 297 9>;
>> +		assigned-clock-parents = <&k3_clks 297 10>;
>> +		assigned-clock-rates = <19200000>;
>> +		num-lanes = <4>;
>> +		#reset-cells = <1>;
>> +		ranges = <0x5050000 0x0 0x5050000 0x10000>,
>> +			<0xa030a00 0x0 0xa030a00 0x40>;
>> +
>> +		wiz4_pll0_refclk: pll0-refclk {
> 	clock@ ?
>> +			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
>> +			clock-output-names = "wiz4_pll0_refclk";
>> +			#clock-cells = <0>;
>> +			assigned-clocks = <&wiz4_pll0_refclk>;
>> +			assigned-clock-parents = <&k3_clks 297 9>;
>> +		};
>> +
>> +		wiz4_pll1_refclk: pll1-refclk {
> 	same?
>> +			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
>> +			clock-output-names = "wiz4_pll1_refclk";
>> +			#clock-cells = <0>;
>> +			assigned-clocks = <&wiz4_pll1_refclk>;
>> +			assigned-clock-parents = <&k3_clks 297 9>;
>> +		};
>> +
>> +		wiz4_refclk_dig: refclk-dig {
> 	same?
>> +			clocks = <&k3_clks 297 9>, <&dummy_cmn_refclk>;
>> +			clock-output-names = "wiz4_refclk_dig";
>> +			#clock-cells = <0>;
>> +			assigned-clocks = <&wiz4_refclk_dig>;
>> +			assigned-clock-parents = <&k3_clks 297 9>;
>> +		};
>> +
>> +		wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div {
> 	same?
>> +			clocks = <&wiz4_refclk_dig>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
> 	same?
>> +			clocks = <&wiz4_pll1_refclk>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		serdes4: serdes at 5050000 {
>> +			/*
>> +			 * Note: we also map DPTX PHY registers as the Torrent
>> +			 * needs to manage those.
>> +			 */
>> +			compatible = "ti,j721e-serdes-10g";
>> +			reg = <0x5050000 0x10000>,
>> +			      <0xa030a00 0x40>; /* DPTX PHY */
>> +			reg-names = "torrent_phy", "dptx_phy";
>> +
>> +			resets = <&serdes_wiz4 0>;
>> +			reset-names = "torrent_reset";
>> +			clocks = <&wiz4_pll0_refclk>;
>> +			clock-names = "refclk";
>> +			#address-cells = <1>;
>> +			#size-cells = <0>;
>> +			torrent_phy_dp: phy at 0 {
>> +				reg = <0>;
>> +				resets = <&serdes_wiz4 1>;
>> +				cdns,phy-type = <PHY_TYPE_DP>;
>> +				cdns,num-lanes = <4>;
>> +				cdns,max-bit-rate = <5400>;
>> +				#phy-cells = <0>;
>> +			};
>> +		};
>> +	};
>> +
> Do you see any impact of the discussions we are having at [1] ?
You mean using wiz or serdes naming all around?

But I think the answer to all the comments is the same: I'm following what's already there for
serdes 0-3 in k3-j721e-main.dtsi, and what's defined in ti,phy-j721e-wiz.yaml.

Kishon is probably better person to answer about changes to the wiz naming.

 Tomi

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