CPU_METHOD_OF_DECLARE() with Linux as non-secure OS
slash.tmp at free.fr
Mon Nov 2 03:55:45 PST 2015
On 02/11/2015 11:17, Russell King - ARM Linux wrote:
> Eg, you could have the FLZ bit set in the L2 cache auxiliary register
> if its wired to a Cortex A9 CPU and the FLZ signal is wired. That
> would be perfectly reasonable, provided the FLZ bit in the Cortex
> A9's control register is disabled when the L2 cache is otherwise
> (I guess I ought to quieten down the pr_err() in that case...)
Based on the pr_err(), I thought it was considered an error, so
I asked the firmware author to leave L2AUX.FLZ cleared, and only
set it just before the cache is enabled, and clear it after the
cache is disabled.
Do you remember why you considered it an error at the time?
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