CPU_METHOD_OF_DECLARE() with Linux as non-secure OS

Russell King - ARM Linux linux at arm.linux.org.uk
Mon Nov 2 02:17:50 PST 2015

On Sat, Oct 31, 2015 at 03:41:57PM +0000, Måns Rullgård wrote:
> The best value to use depends on the workload, so it would be nice to be
> able to control all the purely performance related bits.  I see no
> possible benefit in restricting the non-secure kernel from writing
> these.

For the most case, the auxiliary control register settings are static.
Once the L2 cache is enabled, you can't write to the control register
until the L2 cache is disabled, and you can't sensibly do that on a
running system without taking the system down.

Those which can be tuned at runtime (the prefetch enables) are also
available in the prefetch control register, along with the prefetch

The auxiliary control register is really to do with configuring the
cache to the system its in rather than about performance.

Eg, you could have the FLZ bit set in the L2 cache auxiliary register
if its wired to a Cortex A9 CPU and the FLZ signal is wired.  That
would be perfectly reasonable, provided the FLZ bit in the Cortex
A9's control register is disabled when the L2 cache is otherwise

(I guess I ought to quieten down the pr_err() in that case...)

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