[PATCH] drivers/net/ethoc: add mdio bus support

[Sascha Hauer]

On Wed, May 14, 2014 at 06:59:29PM +0200, Franck Jullien wrote:
> Signed-off-by: Franck Jullien <franck.jullien at gmail.com>

Applied, thanks

Sascha

> ---
>  drivers/net/Kconfig |    1 +
>  drivers/net/ethoc.c |   57 +++++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 58 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 057abd2..7a0d5e1 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -80,6 +80,7 @@ config DRIVER_NET_EP93XX
>  
>  config DRIVER_NET_ETHOC
>  	bool "OpenCores ethernet MAC driver"
> +	select PHYLIB
>  	help
>  	  This option enables support for the OpenCores 10/100 Mbps
>  	  Ethernet MAC core.
> diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
> index b000875..1fb6111 100644
> --- a/drivers/net/ethoc.c
> +++ b/drivers/net/ethoc.c
> @@ -178,6 +178,8 @@ struct ethoc {
>  
>  	u32 num_rx;
>  	u32 cur_rx;
> +
> +	struct mii_bus miibus;
>  };
>  
>  /**
> @@ -481,6 +483,54 @@ static int ethoc_send_packet(struct eth_device *edev, void *packet, int length)
>  	return 0;
>  }
>  
> +static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
> +{
> +	struct ethoc *priv = bus->priv;
> +	u64 start;
> +	u32 data;
> +
> +	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
> +	ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
> +
> +	start = get_time_ns();
> +	while (ethoc_read(priv, MIISTATUS) & MIISTATUS_BUSY) {
> +		if (is_timeout(start, 2 * MSECOND)) {
> +			dev_err(bus->parent, "PHY command timeout\n");
> +			return -EBUSY;
> +		}
> +	}
> +
> +	data = ethoc_read(priv, MIIRX_DATA);
> +
> +	/* reset MII command register */
> +	ethoc_write(priv, MIICOMMAND, 0);
> +
> +	return data;
> +}
> +
> +static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
> +{
> +	struct ethoc *priv = bus->priv;
> +	u64 start;
> +
> +	ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
> +	ethoc_write(priv, MIITX_DATA, val);
> +	ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
> +
> +	start = get_time_ns();
> +	while (ethoc_read(priv, MIISTATUS) & MIISTATUS_BUSY) {
> +		if (is_timeout(start, 2 * MSECOND)) {
> +			dev_err(bus->parent, "PHY command timeout\n");
> +			return -EBUSY;
> +		}
> +	}
> +
> +	/* reset MII command register */
> +	ethoc_write(priv, MIICOMMAND, 0);
> +
> +	return 0;
> +}
> +
>  static int ethoc_probe(struct device_d *dev)
>  {
>  	struct eth_device *edev;
> @@ -493,6 +543,11 @@ static int ethoc_probe(struct device_d *dev)
>  	priv = edev->priv;
>  	priv->iobase = dev_request_mem_region(dev, 0);
>  
> +	priv->miibus.read = ethoc_mdio_read;
> +	priv->miibus.write = ethoc_mdio_write;
> +	priv->miibus.priv = priv;
> +	priv->miibus.parent = dev;
> +
>  	edev->init = ethoc_init_dev;
>  	edev->open = ethoc_open;
>  	edev->send = ethoc_send_packet;
> @@ -503,6 +558,8 @@ static int ethoc_probe(struct device_d *dev)
>  	edev->set_ethaddr = ethoc_set_ethaddr;
>  	edev->parent = dev;
>  
> +	mdiobus_register(&priv->miibus);
> +
>  	eth_register(edev);
>  
>  	return 0;
> -- 
> 1.7.1
> 
> 
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