[PATCH 4/4] Fix checkpatch warnings in DXE and HAL
Eugene Krasnikov
k.eugene.e at gmail.com
Mon Jul 29 14:06:25 EDT 2013
All errors and warnings after running checkpatch were fixed
in following files:
dxe.c
dxe.h
hal.h
Signed-off-by: Eugene Krasnikov <k.eugene.e at gmail.com>
---
dxe.c | 6 ++--
dxe.h | 114 +++++++++++++++++++++++++++++++++++++++++++++---------------------
hal.h | 73 +++++++++++++++++++++++-------------------
3 files changed, 122 insertions(+), 71 deletions(-)
diff --git a/dxe.c b/dxe.c
index 1bde546..3062c09 100644
--- a/dxe.c
+++ b/dxe.c
@@ -33,18 +33,20 @@ void *wcn36xx_dxe_get_next_bd(struct wcn36xx *wcn, bool is_low)
}
static void wcn36xx_dxe_write_register(struct wcn36xx *wcn, int addr, int data)
{
+ wmb();
wcn36xx_dbg(WCN36XX_DBG_DXE,
"wcn36xx_dxe_write_register: addr=%x, data=%x",
addr, data);
- writel(data, wcn->mmio + addr);
+ writel_relaxed(data, wcn->mmio + addr);
}
static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data)
{
- *data = readl(wcn->mmio + addr);
+ *data = readl_relaxed(wcn->mmio + addr);
wcn36xx_dbg(WCN36XX_DBG_DXE,
"wcn36xx_dxe_read_register: addr=%x, data=%x",
addr, *data);
+ rmb();
}
static void wcn36xx_dxe_free_ctl_block(struct wcn36xx_dxe_ch *ch)
diff --git a/dxe.h b/dxe.h
index 16f0b12..858f6d9 100644
--- a/dxe.h
+++ b/dxe.h
@@ -97,38 +97,71 @@ H2H_TEST_RX_TX = DMA2
#define WCN36XX_DXE_TX_HIGH_OFFSET 0x500
#define WCN36XX_DXE_RX_LOW_OFFSET 0x440
#define WCN36XX_DXE_RX_HIGH_OFFSET 0x4C0
+
/* Address of the next DXE descriptor */
#define WCN36XX_DXE_CH_NEXT_DESC_ADDR 0x001C
-#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR)
-#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR)
-#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR)
-#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_NEXT_DESC_ADDR)
+#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_TX_LOW_OFFSET + \
+ WCN36XX_DXE_CH_NEXT_DESC_ADDR)
+#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_TX_HIGH_OFFSET + \
+ WCN36XX_DXE_CH_NEXT_DESC_ADDR)
+#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_RX_LOW_OFFSET + \
+ WCN36XX_DXE_CH_NEXT_DESC_ADDR)
+#define WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_RX_HIGH_OFFSET + \
+ WCN36XX_DXE_CH_NEXT_DESC_ADDR)
/* DXE Descriptor source address */
#define WCN36XX_DXE_CH_SRC_ADDR 0x000C
-#define WCN36XX_DXE_CH_SRC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_SRC_ADDR)
-#define WCN36XX_DXE_CH_SRC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_SRC_ADDR)
+#define WCN36XX_DXE_CH_SRC_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_RX_LOW_OFFSET + \
+ WCN36XX_DXE_CH_SRC_ADDR)
+#define WCN36XX_DXE_CH_SRC_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_RX_HIGH_OFFSET + \
+ WCN36XX_DXE_CH_SRC_ADDR)
/* DXE Descriptor address destination address */
#define WCN36XX_DXE_CH_DEST_ADDR 0x0014
-#define WCN36XX_DXE_CH_DEST_ADDR_TX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET + WCN36XX_DXE_CH_DEST_ADDR)
-#define WCN36XX_DXE_CH_DEST_ADDR_TX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET + WCN36XX_DXE_CH_DEST_ADDR)
-#define WCN36XX_DXE_CH_DEST_ADDR_RX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_DEST_ADDR)
-#define WCN36XX_DXE_CH_DEST_ADDR_RX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_DEST_ADDR)
+#define WCN36XX_DXE_CH_DEST_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_TX_LOW_OFFSET + \
+ WCN36XX_DXE_CH_DEST_ADDR)
+#define WCN36XX_DXE_CH_DEST_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_TX_HIGH_OFFSET + \
+ WCN36XX_DXE_CH_DEST_ADDR)
+#define WCN36XX_DXE_CH_DEST_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_RX_LOW_OFFSET + \
+ WCN36XX_DXE_CH_DEST_ADDR)
+#define WCN36XX_DXE_CH_DEST_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_RX_HIGH_OFFSET + \
+ WCN36XX_DXE_CH_DEST_ADDR)
/* Interrupt status */
#define WCN36XX_DXE_CH_STATUS_REG_ADDR 0x0004
-#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR)
-#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR)
-#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR)
-#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET + WCN36XX_DXE_CH_STATUS_REG_ADDR)
+#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_TX_LOW_OFFSET + \
+ WCN36XX_DXE_CH_STATUS_REG_ADDR)
+#define WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_TX_HIGH_OFFSET + \
+ WCN36XX_DXE_CH_STATUS_REG_ADDR)
+#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_L (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_RX_LOW_OFFSET + \
+ WCN36XX_DXE_CH_STATUS_REG_ADDR)
+#define WCN36XX_DXE_CH_STATUS_REG_ADDR_RX_H (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_RX_HIGH_OFFSET + \
+ WCN36XX_DXE_CH_STATUS_REG_ADDR)
/* DXE default control register */
-#define WCN36XX_DXE_REG_CTL_RX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_LOW_OFFSET)
-#define WCN36XX_DXE_REG_CTL_RX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_RX_HIGH_OFFSET)
-#define WCN36XX_DXE_REG_CTL_TX_H (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_HIGH_OFFSET)
-#define WCN36XX_DXE_REG_CTL_TX_L (WCN36XX_DXE_MEM_REG + WCN36XX_DXE_TX_LOW_OFFSET)
+#define WCN36XX_DXE_REG_CTL_RX_L (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_RX_LOW_OFFSET)
+#define WCN36XX_DXE_REG_CTL_RX_H (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_RX_HIGH_OFFSET)
+#define WCN36XX_DXE_REG_CTL_TX_H (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_TX_HIGH_OFFSET)
+#define WCN36XX_DXE_REG_CTL_TX_L (WCN36XX_DXE_MEM_REG + \
+ WCN36XX_DXE_TX_LOW_OFFSET)
#define WCN36XX_SMSM_WLAN_TX_ENABLE 0x00000400
#define WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY 0x00000200
@@ -158,26 +191,35 @@ enum wcn36xx_dxe_ch_desc_num {
WCN36XX_DXE_CH_DESC_NUMB_RX_H = 40
};
+/**
+ * struct wcn36xx_dxe_desc - describes descriptor of one DXE buffer
+ *
+ * @ctrl: is a union that consists of following bits:
+ * union {
+ * u32 valid :1; //0 = DMA stop, 1 = DMA continue with this
+ * //descriptor
+ * u32 transfer_type :2; //0 = Host to Host space
+ * u32 eop :1; //End of Packet
+ * u32 bd_handling :1; //if transferType = Host to BMU, then 0
+ * // means first 128 bytes contain BD, and 1
+ * // means create new empty BD
+ * u32 siq :1; // SIQ
+ * u32 diq :1; // DIQ
+ * u32 pdu_rel :1; //0 = don't release BD and PDUs when done,
+ * // 1 = release them
+ * u32 bthld_sel :4; //BMU Threshold Select
+ * u32 prio :3; //Specifies the priority level to use for
+ * // the transfer
+ * u32 stop_channel :1; //1 = DMA stops processing further, channel
+ * //requires re-enabling after this
+ * u32 intr :1; //Interrupt on Descriptor Done
+ * u32 rsvd :1; //reserved
+ * u32 size :14;//14 bits used - ignored for BMU transfers,
+ * //only used for host to host transfers?
+ * } ctrl;
+ */
struct wcn36xx_dxe_desc {
u32 ctrl;
-/*
- //TODO: Drop these, the hard coded values above and start using hal.h
- union {
- u32 valid :1; //0 = DMA stop, 1 = DMA continue with this descriptor
- u32 transfer_type :2; //0 = Host to Host space
- u32 eop :1; //End of Packet
- u32 bd_handling :1; //if transferType = Host to BMU, then 0 means first 128 bytes contain BD, and 1 means create new empty BD
- u32 siq :1; // SIQ
- u32 diq :1; // DIQ
- u32 pdu_rel :1; //0 = don't release BD and PDUs when done, 1 = release them
- u32 bthld_sel :4; //BMU Threshold Select
- u32 prio :3; //Specifies the priority level to use for the transfer
- u32 stop_channel :1; //1 = DMA stops processing further, channel requires re-enabling after this
- u32 intr :1; //Interrupt on Descriptor Done
- u32 rsvd :1; //reserved
- u32 size :14; //14 bits used - ignored for BMU transfers, only used for host to host transfers?
- } desc_ctl;
-*/
u32 fr_len;
u32 src_addr_l;
diff --git a/hal.h b/hal.h
index 2b9f1b9..07329f9 100644
--- a/hal.h
+++ b/hal.h
@@ -357,7 +357,8 @@ enum wcn36xx_hal_host_msg_type {
enum wcn36xx_hal_host_msg_version {
WCN36XX_HAL_MSG_VERSION0 = 0,
WCN36XX_HAL_MSG_VERSION1 = 1,
- WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION = 0x7FFF, /*define as 2 bytes data */
+ /* define as 2 bytes data */
+ WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION = 0x7FFF,
WCN36XX_HAL_MSG_VERSION_MAX_FIELD = WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION
};
@@ -396,7 +397,7 @@ enum phy_chan_bond_state {
/* 40MHz IF bandwidth centered on IF carrier */
PHY_DOUBLE_CHANNEL_CENTERED = 2,
- /* 40MHz IF bandwidth with higher 20MHz supporting the primary channel */
+ /* 40MHz IF bandwidth with higher 20MHz supporting the primary ch */
PHY_DOUBLE_CHANNEL_HIGH_PRIMARY = 3,
/* 20/40MHZ offset LOW 40/80MHZ offset CENTERED */
@@ -672,7 +673,7 @@ struct wcn36xx_hal_cfg {
* in shared header file between UMAC and HAL.*/
u16 id;
- /* Length of the Cfg. This parameter is used to go to next cfg
+ /* Length of the Cfg. This parameter is used to go to next cfg
* in the TLV format.*/
u16 len;
@@ -693,7 +694,7 @@ struct wcn36xx_hal_mac_start_parameters {
/* Length of the config buffer */
u32 len;
- /* Following this there is a TLV formatted buffer of length
+ /* Following this there is a TLV formatted buffer of length
* "len" bytes containing all config values.
* The TLV is expected to be formatted like this:
* 0 15 31 31+CFG_LEN-1 length-1
@@ -1085,7 +1086,7 @@ struct wcn36xx_hal_config_sta_params {
/* RIFS mode 0 - NA, 1 - Allowed */
u8 rifs_mode;
- /* L-SIG TXOP Protection mechanism
+ /* L-SIG TXOP Protection mechanism
0 - No Support, 1 - Supported
SG - there is global field */
u8 lsig_txop_protection;
@@ -1106,7 +1107,7 @@ struct wcn36xx_hal_config_sta_params {
/* Short GI support for 20Mhz packets */
u8 sgi_20Mhz;
- // TODO move this parameter to the end for 3680
+ /* TODO move this parameter to the end for 3680 */
/* These rates are the intersection of peer and self capabilities. */
struct wcn36xx_hal_supported_rates supported_rates;
@@ -1117,8 +1118,8 @@ struct wcn36xx_hal_config_sta_params {
u32 encrypt_type;
/* HAL should update the existing STA entry, if this flag is set. UMAC
- will set this flag in case of RE-ASSOC, where we want to reuse the old
- STA ID. 0 = Add, 1 = Update */
+ will set this flag in case of RE-ASSOC, where we want to reuse the
+ old STA ID. 0 = Add, 1 = Update */
u8 action;
/* U-APSD Flags: 1b per AC. Encoded as follows:
@@ -1159,9 +1160,9 @@ struct wcn36xx_hal_config_sta_params {
u8 p2p;
- // TODO add this parameter for 3680.
+ /* TODO add this parameter for 3680. */
/* Reserved to align next field on a dword boundary */
- //u8 reserved;
+ /* u8 reserved; */
} __packed;
struct wcn36xx_hal_config_sta_req_msg {
@@ -1200,7 +1201,7 @@ struct wcn36xx_hal_config_sta_params_v1 {
/* RIFS mode 0 - NA, 1 - Allowed */
u8 rifs_mode;
- /* L-SIG TXOP Protection mechanism
+ /* L-SIG TXOP Protection mechanism
0 - No Support, 1 - Supported
SG - there is global field */
u8 lsig_txop_protection;
@@ -1228,8 +1229,8 @@ struct wcn36xx_hal_config_sta_params_v1 {
u32 encrypt_type;
/* HAL should update the existing STA entry, if this flag is set. UMAC
- will set this flag in case of RE-ASSOC, where we want to reuse the old
- STA ID. 0 = Add, 1 = Update */
+ will set this flag in case of RE-ASSOC, where we want to reuse the
+ old STA ID. 0 = Add, 1 = Update */
u8 action;
/* U-APSD Flags: 1b per AC. Encoded as follows:
@@ -1389,7 +1390,8 @@ struct wcn36xx_hal_mac_ssid {
enum wcn36xx_hal_con_mode {
WCN36XX_HAL_STA_MODE = 0,
- /* to support softAp mode . This is misleading. It means AP MODE only. */
+ /* to support softAp mode . This is misleading.
+ It means AP MODE only. */
WCN36XX_HAL_STA_SAP_MODE = 1,
WCN36XX_HAL_P2P_CLIENT_MODE,
@@ -1472,7 +1474,7 @@ struct wcn36xx_hal_config_bss_params {
/* Reserved to align next field on a dword boundary */
u8 reserved;
- //TODO move sta to the end for 3680
+ /* TODO move sta to the end for 3680 */
/* Context of the station being added in HW
* Add a STA entry for "itself" -
*
@@ -2030,8 +2032,7 @@ struct update_edca_params_rsp_msg {
u32 status;
};
-struct dpu_stats_params
-{
+struct dpu_stats_params {
/* Index of STA to which the statistics */
u16 sta_index;
@@ -2076,7 +2077,7 @@ struct ani_summary_stats_info {
/* Total number of packets(per AC) that were successfully
* transmitted (with and without retries, including multi-cast,
* broadcast) */
- u32 tx_frm_cnt[4];
+ u32 tx_frm_cnt[4];
/* Total number of packets that were successfully received (after
* appropriate filter rules including multi-cast, broadcast) */
@@ -2534,7 +2535,7 @@ struct wcn36xx_hal_trigger_ba_req_msg {
/* Session Id */
u8 session_id;
- /* baCandidateCnt is followed by trigger BA
+ /* baCandidateCnt is followed by trigger BA
* Candidate List(tTriggerBaCandidate)
*/
u16 candidate_cnt;
@@ -2550,7 +2551,7 @@ struct wcn36xx_hal_trigger_ba_rsp_msg {
/* success or failure */
u32 status;
- /* baCandidateCnt is followed by trigger BA
+ /* baCandidateCnt is followed by trigger BA
* Rsp Candidate List(tTriggerRspBaCandidate)
*/
u16 candidate_cnt;
@@ -2624,8 +2625,9 @@ struct set_key_done_msg {
};
struct wcn36xx_hal_nv_img_download_req_msg {
- /* Note: The length specified in wcn36xx_hal_nv_img_download_req_msg messages
- * should be header.len = sizeof(wcn36xx_hal_nv_img_download_req_msg) +
+ /* Note: The length specified in wcn36xx_hal_nv_img_download_req_msg
+ * messages should be
+ * header.len = sizeof(wcn36xx_hal_nv_img_download_req_msg) +
* nv_img_buffer_size */
struct wcn36xx_hal_msg_header header;
@@ -2642,8 +2644,8 @@ struct wcn36xx_hal_nv_img_download_req_msg {
/* Is this the last fragment? When set to 1 it indicates that no
* more fragments will be sent by UMAC and HAL can concatenate all
* the NV blobs rcvd & proceed with the parsing. HAL would generate
- * a WCN36XX_HAL_DOWNLOAD_NV_RSP to the WCN36XX_HAL_DOWNLOAD_NV_REQ after
- * it receives each fragment */
+ * a WCN36XX_HAL_DOWNLOAD_NV_RSP to the WCN36XX_HAL_DOWNLOAD_NV_REQ
+ * after it receives each fragment */
u16 last_fragment;
/* NV Image size (number of bytes) */
@@ -2960,7 +2962,9 @@ struct wcn36xx_hal_missed_beacon_ind_msg {
/* Beacon Filtering data structures */
-/* The above structure would be followed by multiple of below mentioned structure */
+/* The above structure would be followed by multiple of below mentioned
+ * structure
+ */
struct beacon_filter_ie {
u8 element_id;
u8 check_ie_presence;
@@ -2995,7 +2999,8 @@ struct wcn36xx_hal_rem_bcn_filter_req {
#define WCN36XX_HAL_OFFLOAD_DISABLE 0
#define WCN36XX_HAL_OFFLOAD_ENABLE 1
#define WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE 0x2
-#define WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE (HAL_OFFLOAD_ENABLE|HAL_OFFLOAD_BCAST_FILTER_ENABLE)
+#define WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE \
+ (HAL_OFFLOAD_ENABLE|HAL_OFFLOAD_BCAST_FILTER_ENABLE)
struct wcn36xx_hal_ns_offload_params {
u8 src_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
@@ -4165,7 +4170,8 @@ struct wcn36xx_hal_rcv_flt_pkt_match_cnt_rsp_msg {
u32 status;
u32 match_count;
- struct wcn36xx_hal_rcv_flt_pkt_match_cnt matches[WCN36XX_HAL_MAX_NUM_FILTERS];
+ struct wcn36xx_hal_rcv_flt_pkt_match_cnt
+ matches[WCN36XX_HAL_MAX_NUM_FILTERS];
u8 bss_index;
};
@@ -4448,8 +4454,8 @@ struct dhcp_ind_status {
*
* WCN36XX_HAL_THERMAL_MITIGATION_MODE_0 - Based on AMPDU disabling aggregation
*
- * WCN36XX_HAL_THERMAL_MITIGATION_MODE_1 - Based on AMPDU disabling aggregation and
- * reducing transmit power
+ * WCN36XX_HAL_THERMAL_MITIGATION_MODE_1 - Based on AMPDU disabling aggregation
+ * and reducing transmit power
*
* WCN36XX_HAL_THERMAL_MITIGATION_MODE_2 - Not supported */
enum wcn36xx_hal_thermal_mitigation_mode_type {
@@ -4463,11 +4469,12 @@ enum wcn36xx_hal_thermal_mitigation_mode_type {
/*
* Thermal Mitigation level.
- * Note the levels are incremental i.e WCN36XX_HAL_THERMAL_MITIGATION_LEVEL_2 =
- * WCN36XX_HAL_THERMAL_MITIGATION_LEVEL_0 + WCN36XX_HAL_THERMAL_MITIGATION_LEVEL_1
+ * Note the levels are incremental i.e WCN36XX_HAL_THERMAL_MITIGATION_LEVEL_2 =
+ * WCN36XX_HAL_THERMAL_MITIGATION_LEVEL_0 +
+ * WCN36XX_HAL_THERMAL_MITIGATION_LEVEL_1
*
- * WCN36XX_HAL_THERMAL_MITIGATION_LEVEL_0 - lowest level of thermal mitigation. This
- * level indicates normal mode of operation
+ * WCN36XX_HAL_THERMAL_MITIGATION_LEVEL_0 - lowest level of thermal mitigation.
+ * This level indicates normal mode of operation
*
* WCN36XX_HAL_THERMAL_MITIGATION_LEVEL_1 - 1st level of thermal mitigation
*
--
1.8.2.2
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