How many colours does the ARC cache have?

[Vineet Gupta]

On 2/10/23 09:06, Matthew Wilcox wrote:
> I see a discrepancy here ...
>
> arch/arc/include/asm/shmparam.h:
> /* Handle upto 2 cache bins */
> #define SHMLBA  (2 * PAGE_SIZE)
>
> arch/arc/include/asm/cacheflush.h:
> #define CACHE_COLORS_NUM        4

The initial aliasing dcache support assumed 2 colors but was later 
bumped to 4, w/o making the adjustment in shmparam.h

> (there are some other problems with the arc cache flushing code;

The VIPT aliasing config (which is pretty much dead and unused) or 
regular parts ?


> I'm working on patches to address them, but those are things I understand a
> little better.  I know nothing about the ARC architecture itself)

Legacy ARC700 cpus had VIPT D$. The cache size was configurable by Soc 
builder and the specific geometry could yield an aliasing configuration 
(e.g. standard page size 8K, 4 way set associative D$: so D$ > 32K were 
aliasing and needed CONFIG_ARC_CACHE_VIPT_ALIASING). Although there was 
ever only 1 customer who taped out an aliasing cache config.

The newer ARC HS cores have PIPT D$ and thus don't need the aliasing 
support.

FWIW we could rip out all the VIPT aliasing code as I don't think it is 
needed anymore. @Alexey can you confirm ?

-Vineet