[PATCH] ARC: clk: introduce HSDKv1 pll driver

[Stephen Boyd]

On 07/27, Vineet Gupta wrote:
> Hi Stephen,
> 
> On 07/14/2017 09:01 PM, Eugeniy Paltsev wrote:
> >HSDKv1 boards manages it's clocks using various PLLs. These PLL has same
> >dividers and corresponding control registers mapped to different addresses.
> >So we add one common driver for such PLLs.
> >
> >Each PLL on HSDK board consist of three dividers: IDIV, FBDIV and
> >ODIV. Output clock value is managed using these dividers.
> >
> >We add pre-defined tables with supported rate values and appropriate
> >configurations of IDIV, FBDIV and ODIV for each value.
> >
> >As of today we add support for PLLs that generate clock for the
> >HSDKv1 arc cpus, system, ddr, AXI tunnel and hdmi.
> >
> >By this patch we add support for several plls (arc cpus pll and others),
> >so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
> >and regular probing for others plls.
> >
> >Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev at synopsys.com>
> 
> Gentle ping, any chance you could look at this sometime.
> 
> Thx,

Yes it's in the queue. Probably get to it tomorrow.

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