[PATCH] arc: arcv2: cache: Explicitly set MSB counterpart of region ops addresses

[Vineet Gupta]

On 08/02/2017 01:33 PM, Alexey Brodkin wrote:
>
>>> -	write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));
>>> -	write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
>>> +	end = paddr + sz + l2_line_sz - 1;
>>> +	write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
>>> +	write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
>>> +	write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
>>> +	write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
>> Are these registers present even if PAE is not configured in hardware ?
> Apparently no :(
>
> I did test it on AXS103 but just now realized its latest firmware has PAE40.
> Retested on older firmware (still with HS 2.1) without PAE and indeed those
> AUX registers are not implemented:
> ----------------------->8----------------------
> ...
>
> So I'll respin this patch with conditional setup of those regs
> depending on PAE40 presence.

And please also do another patch which converts the existing is_pae40_enabled() 
calls to is_pae40_exists() or somesuch, as apparently these regs needs to be 
cleared if hw has PAE and kernel not using PAE is immaterial.