[PATCH] ARM: dts: bcm2711: Add the missing L1/L2 cache information

[Florian Fainelli]

On 12/21/2021 2:48 PM, Richard Schleich wrote:
> This patch fixes the kernel warning
> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
> for the bcm2711 on newer kernel versions.
> 
> Signed-off-by: Richard Schleich <rs at noreya.tech>

Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, 
thanks!

I did remove the comments that were not helpful for the 'd-cache-size', 
'd-cache-line-size', 'i-cache-size' and 'i-cache-line-size'  since they 
are self explanatory.
-- 
Florian