[PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information

Florian Fainelli f.fainelli at gmail.com
Mon Jan 31 16:29:11 PST 2022

On 1/31/2022 4:24 PM, Florian Fainelli wrote:
> On Sat, 18 Dec 2021 21:00:09 +0100, Richard Schleich <rs at noreya.tech> wrote:
>> This patch fixes the kernel warning
>> "cacheinfo: Unable to detect cache hierarchy for CPU 0"
>> for the bcm2837 on newer kernel versions.
>> Signed-off-by: Richard Schleich <rs at noreya.tech>
>> ---
> Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!

I did remove the comments that were not helpful for the 'd-cache-size', 
'd-cache-line-size', 'i-cache-size' and 'i-cache-line-size'  since they 
are self explanatory.


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