[alsa-devel] [PATCH 0/3] ASoC: Enable a new IC master mode: bcm2835<=>IC<=>cs42xx8

[Matt Flax]

On 25/03/17 06:09, Mark Brown wrote:
> On Wed, Mar 22, 2017 at 11:04:34PM +1100, Matt Flax wrote:
>> On 22/03/17 20:43, Charles Keepax wrote:
>>> Are we saying that what gets transmitted on the bus is neither valid
>>> I2S or DSP mode data? But as you have your custom hardware block in
>>> the middle it interprets this data correctly and converts it to a
>>> regular bus format on the other side that goes to the CODEC?
>> Yes, essentially there is translation between the two data word edge
>> triggered ABP (the bcm2835's PCM block) and a Cirrus Logic TDM codec.
> Could you please be concrete about what the two formats you're talking
> about here are and how these differences are observable on the wire?  I
> don't know what "two data word edge triggered ABP" means.
On the codec side it is a regular TDM stream.
On the SoC side, two channels  are arbitrarily offset from a PCM frame 
sync clock (PCM_FS) leading edge. I have chosen to have 64 bits per 
frame with 1 bit offset for the first word (from the leading edge) and 
33 bits offset (from the leading edge) for the second word. This 
resembles I2S, but it doesn't have to for the bcm2835.

In more detail ...
The bcm2835's flexible PCM hardware (serialiser+APB) is set up to handle 
two words at a time in/out from a 64 word FIFO buffers. The serialiser 
loads and unloads two registers according to offsets from the PCM_FS 
clock's leading edge. The APB interface is responsible for (un)loading 
the 64 word FIFO buffer to/from memory - with DMA I guess.

thanks
Matt