[PATCH 5/6] clk: bcm2835: correctly enable fractional clock support

Martin Sperl kernel at martin.sperl.org
Mon Feb 29 21:52:46 PST 2016

> On 01.03.2016, at 00:44, Eric Anholt <eric at anholt.net> wrote:
> Once again, trusting the docs turns out to be a bad idea.  You're right,
> the non-MASH clocks *do* have a bit 9 to enable fractional mode.  Sigh.
> So, this patch is:
> Reviewed-by: Eric Anholt <eric at anholt.net>

The only really reliable “docs” on registers I have found outside
of probably signing a NDA are those header files for the VC4 provided
by broadcom. 

That is why I have taken the effort to translate those into something
much more easily readable/searchable (i.e html pages on the web).

And that is where I have “guessed” all the information on the clock
tree structure.

The main thing that is sometimes missing from those documents is
some extra context like: what is that pllt clock with a mux of
8 parent clocks (not 4 or 16 as typical) and what do those
corresponding 4 counter really do?



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