[PATCH V4 1/7] clk: bcm2835: the minimum clock divider is 2
eric at anholt.net
Fri Feb 12 16:28:54 PST 2016
Martin Sperl <kernel at martin.sperl.org> writes:
> On 02.02.2016 00:15, Eric Anholt wrote:
>> kernel at martin.sperl.org writes:
>>> From: Martin Sperl <kernel at martin.sperl.org>
>>> Testing with different clock divider values has shown
>>> that (at least for the PCM clock) the clock divider
>>> has to be at least 2, otherwise the clock will not
>>> output a signal.
>> For a MASH clock (PWM, PCM, SLIMBUS, but not the others), the minimum
>> integer component of the divider is:
>> mash 0: 1
>> mash 1: 2
>> mash 2: 3
>> mash 3: 5
> I know that that is what the datasheet says - see also the errata:
> Experimentation has show that a divider between 1 and 1 + 4095 / 4096
> does not provide any output PCM clock - only 2 and above does work for
> mash = 0, 1, 2 or 3.
> Example: Requesting 12288000Hz (=192kHz at 64bit) with the 19.2Mhz
> oscillator results in a divider of: 1 + 2304 / 4096 and this does not
> give a clock output.
> See the report by hiassoft here:
> (note that it also applies to mash = 0, but there may be no comment on
> this fact in this thread)
> Note that there is patch 7 that implements the above "mash" limits
> for a divider and downgrades to a lower mash level if the divider
> does not qualify.
I do see "2, 2, 3, 5" being used as the minimum dividers used for mash
clocks in the firmware's clock setup. So, as long as you limit this to
the MASH clocks, I think you're right.
What I'd expect of this series as a respin:
1) Fix setup of existing MASH clocks
- Mark the few existing MASH clocks as being MASH.
- Apply MASH integer divider limits to MASH clocks.
- Set the MASH field on MASH clocks.
2) Add PCM clock
If you want to add some other clocks that are definitely the same kinds
of clock generators and where we have known parents for them, that's
fine with me.
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