[PATCH V4 1/7] clk: bcm2835: the minimum clock divider is 2

[Eric Anholt]

kernel at martin.sperl.org writes:

> From: Martin Sperl <kernel at martin.sperl.org>
>
> Testing with different clock divider values has shown
> that (at least for the PCM clock) the clock divider
> has to be at least 2, otherwise the clock will not
> output a signal.

For a MASH clock (PWM, PCM, SLIMBUS, but not the others), the minimum
integer component of the divider is:

mash 0: 1
mash 1: 2
mash 2: 3
mash 3: 5
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