[PATCH] arm64: dts: rockchip: move rk3399-sapphire PCIe to excavator baseboard

[Shawn Lin]

On 2018/2/27 2:57, Vicente Bergas wrote:
> The PCIe signals are routed through the connector to the baseboard.
> 
> Signed-off-by: Vicente Bergas <vicencb at gmail.com>
> Tested-by: Vicente Bergas <vicencb at gmail.com>
> ---
>   .../arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts | 15 +++++++++++++++
>   arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi         | 15 ---------------
>   2 files changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
> index 56952d1a3fb8..4d47150d6862 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts
> @@ -190,6 +190,21 @@
>   	status = "okay";
>   };
>   
> +&pcie_phy {
> +	status = "okay";
> +};
> +
> +&pcie0 {
> +	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
> +	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
> +	assigned-clock-rates = <100000000>;

Ah, could you remove these assigned-clock* as well?
reference clock is needed for pcie_phy, not pcie controller.
Actually pcie_phy doesn't need this since rk3399 clock driver
already take care of this.

Otherwise,
Reviewed-by: Shawn Lin <shawn.lin at rock-chips.com>


> +	ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
> +	num-lanes = <4>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pcie_clkreqn_cpm>;
> +	status = "okay";
> +};
> +
>   &pinctrl {
>   	sdio-pwrseq {
>   		wifi_enable_h: wifi-enable-h {
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
> index e5b0369e197f..8c7db887f2cf 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi
> @@ -471,21 +471,6 @@
>   	gpio1830-supply = <&vcc_3v0>;
>   };
>   
> -&pcie_phy {
> -	status = "okay";
> -};
> -
> -&pcie0 {
> -	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
> -	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
> -	assigned-clock-rates = <100000000>;
> -	ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
> -	num-lanes = <4>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pcie_clkreqn_cpm>;
> -	status = "okay";
> -};
> -
>   &pmu_io_domains {
>   	pmu1830-supply = <&vcc_3v0>;
>   	status = "okay";
>