[PATCH 7/9] riscv: dts: ultrarisc: add Rongda M0 board device tree

[Jia Wang]

On 2026-05-15 11:28 +0100, Conor Dooley wrote:
> On Fri, May 15, 2026 at 09:18:03AM +0800, Jia Wang wrote:
> > Rongda M0 is an mATX motherboard based on the UltraRISC DP1000 SoC.
> > 
> > Signed-off-by: Jia Wang <wangjia at ultrarisc.com>
> > ---
> >  arch/riscv/boot/dts/Makefile                       |   1 +
> >  arch/riscv/boot/dts/ultrarisc/Makefile             |   2 +
> >  .../dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi    |  85 ++++++++++++++++
> >  arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts | 111 +++++++++++++++++++++
> >  4 files changed, 199 insertions(+)
> > 
> > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> > index 69d8751fb17c..702882974251 100644
> > --- a/arch/riscv/boot/dts/Makefile
> > +++ b/arch/riscv/boot/dts/Makefile
> > @@ -12,3 +12,4 @@ subdir-y += spacemit
> >  subdir-y += starfive
> >  subdir-y += tenstorrent
> >  subdir-y += thead
> > +subdir-y += ultrarisc
> > diff --git a/arch/riscv/boot/dts/ultrarisc/Makefile b/arch/riscv/boot/dts/ultrarisc/Makefile
> > new file mode 100644
> > index 000000000000..d01a770d3cba
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/ultrarisc/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_ARCH_ULTRARISC) += dp1000-rongda-m0.dtb
> > diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi
> > new file mode 100644
> > index 000000000000..101b416b1079
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0-pinctrl.dtsi
> > @@ -0,0 +1,85 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
> > + */
> > +
> > +#include "dp1000.dtsi"
> > +
> > +&pmx0 {
> > +	i2c0_pins: i2c0-pins {
> > +		pins = "PA12", "PA13";
> > +		function = "func0";
> 
> This is what I meant about func0 btw, and having this be "i2c" etc instead.

Right, agreed. I will use semantic function names instead.

> > diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts
> > new file mode 100644
> > index 000000000000..6f72d60ad55e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/ultrarisc/dp1000-rongda-m0.dts
> > @@ -0,0 +1,111 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright(C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
> > + */
> > +
> > +#include "dp1000-rongda-m0-pinctrl.dtsi"
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > +	model = "Rongda M0 Board";
> > +	compatible = "rongda,m0", "ultrarisc,dp1000";
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart1;
> > +		serial2 = &uart2;
> > +		serial3 = &uart3;
> > +	};
> > +
> > +	chosen {
> > +		stdout-path = "serial0:115200n8";
> > +	};
> > +
> > +	gpio-poweroff {
> > +		compatible = "gpio-poweroff";
> > +		gpios = <&gpio_b 0 GPIO_ACTIVE_HIGH>;
> > +		active-delay-ms = <100>;
> > +
> > +		status = "disabled";
> 
> Why bother adding the nodes if they are disabled? What enables them?
> 

Understood. Since the board uses the OpenSBI SRST extension for
reset/poweroff, these GPIO nodes are unused and do not need to appear in
the DTS.

I'll drop them in the next revision.

> > +	};
> > +
> > +	gpio-restart {
> > +		compatible = "gpio-restart";
> > +		gpios = <&gpio_b 1 GPIO_ACTIVE_HIGH>;
> > +		active-delay = <100>;
> > +
> > +		status = "disabled";
> > +	};
> > +};
> > +
> > +&i2c0 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&i2c0_pins>;
> > +};
> > +
> > +&i2c1 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&i2c1_pins>;
> > +};
> > +
> > +&i2c2 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&i2c2_pins>;
> > +
> > +	rtc at 32 {
> > +		compatible = "whwave,sd3078";
> > +		reg = <0x32>;
> > +	};
> > +};
> > +
> > +&i2c3 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&i2c3_pins>;
> > +};
> > +
> > +&spi0 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&spi0_pins>;
> > +};
> > +
> > +&spi1 {
> > +	num-cs = <1>;
> 
> Why is num-cs set at the board level here?
>

`num-cs` is set at the board level because it reflects board wiring, not
the controller capability. On Rongda M0 only one SPI1 CS line is routed,
so the board DTS restricts `num-cs` to 1.

> > +
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&spi1_pins>;
> > +};
> > +
> > +&uart0 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&uart0_pins>;
> > +};
> > +
> > +&uart1 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&uart1_pins>;
> > +};
> > +
> > +&uart2 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&uart2_pins>;
> > +};
> > +
> > +&ethernet {
> > +	phy-handle = <&phy0>;
> > +	/*
> > +	 * YT8531 RGMII timing on this board requires no PHY internal delays.
> > +	 * Using "rgmii-id" together with rx/tx-internal-delay-ps results in RX CRC
> > +	 * errors and no usable traffic, so keep plain "rgmii" here.
> > +	 */
> > +	phy-mode = "rgmii";
> > +
> > +	mdio {
> > +		compatible = "snps,dwmac-mdio";
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		phy0: phy at 0 {
> > +			reg = <0x00>;
> > +		};
> > +	};
> > +};
> > 
> > -- 
> > 2.34.1
> > 

Best Regards,
Jia Wang