[PATCH 7/7] iommu/riscv: Add NAPOT range invalidation support

[Tomasz Jeznach]

On Tue, May 5, 2026 at 3:47 PM Andrew Jones
<andrew.jones at oss.qualcomm.com> wrote:
>
> On Fri, Apr 10, 2026 at 12:57:08PM -0300, Jason Gunthorpe wrote:
> > Use the RISC-V IOMMU Address Range Invalidation extension
> > (capabilities.S, spec section 9.3) to invalidate an IOVA range with
> > a single IOTINVAL.VMA command using NAPOT-encoded addressing.
> >
> > One iommu_iotlb_gather maps to one NAPOT invalidation command. The
> > smallest power-of-two aligned range covering the gather is used since
> > over-invalidation is always safe.
> >
> > S and NL seem to be orthogonal in the spec, so if NL is not
> > supported then global invalidation is probably always going to happen
> > as wiping a large range without a table change is not common.
> >
> > Signed-off-by: Jason Gunthorpe <jgg at nvidia.com>
> > ---
> >  drivers/iommu/riscv/iommu-bits.h | 17 +++++++++++++
> >  drivers/iommu/riscv/iommu.c      | 43 +++++++++++++++++++++++++++-----
> >  2 files changed, 54 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/iommu/riscv/iommu-bits.h b/drivers/iommu/riscv/iommu-bits.h
> > index f01b49ac815586..32b3ad3ac9ae59 100644
> > --- a/drivers/iommu/riscv/iommu-bits.h
> > +++ b/drivers/iommu/riscv/iommu-bits.h
> > @@ -64,6 +64,7 @@
> >  #define RISCV_IOMMU_CAPABILITIES_PD17                BIT_ULL(39)
> >  #define RISCV_IOMMU_CAPABILITIES_PD20                BIT_ULL(40)
> >  #define RISCV_IOMMU_CAPABILITIES_NL          BIT_ULL(42)
> > +#define RISCV_IOMMU_CAPABILITIES_S           BIT_ULL(43)
> >
> >  /**
> >   * enum riscv_iommu_igs_settings - Interrupt Generation Support Settings
> > @@ -475,6 +476,7 @@ struct riscv_iommu_command {
> >  #define RISCV_IOMMU_CMD_IOTINVAL_GV          BIT_ULL(33)
> >  #define RISCV_IOMMU_CMD_IOTINVAL_GSCID               GENMASK_ULL(59, 44)
> >  #define RISCV_IOMMU_CMD_IOTINVAL_NL          BIT_ULL(34)
> > +#define RISCV_IOMMU_CMD_IOTINVAL_S           BIT_ULL(9)
>
> We should add a comment here that this is actually bit 73, i.e.
>
> #define RISCV_IOMMU_CMD_IOTINVAL_S           BIT_ULL(9) /* bit 73 (dword1 bit 9) */
>
> because...
>
> >  /* dword1[61:10] is the 4K-aligned page address */
> >  #define RISCV_IOMMU_CMD_IOTINVAL_ADDR                GENMASK_ULL(61, 10)
> >
> > @@ -731,6 +733,21 @@ static inline void riscv_iommu_cmd_inval_set_nl(struct riscv_iommu_command *cmd)
> >       cmd->dword0 |= RISCV_IOMMU_CMD_IOTINVAL_NL;
> >  }
> >
> > +/*
> > + * Set NAPOT-encoded address for range invalidation (S=1).
> > + * sz_lg2: log2 of total range in bytes, must be >= 13 (8KiB, 2 pages).
> > + * addr must be naturally aligned to 2^sz_lg2.
> > + */
> > +static inline void riscv_iommu_cmd_inval_set_napot(
> > +     struct riscv_iommu_command *cmd, u64 addr, unsigned int sz_lg2)
> > +{
> > +     u64 pfn = addr >> 12;
> > +
> > +     pfn |= BIT_U64(sz_lg2 - 13) - 1;
> > +     cmd->dword1 = FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, pfn);
> > +     cmd->dword0 |= RISCV_IOMMU_CMD_IOTINVAL_AV | RISCV_IOMMU_CMD_IOTINVAL_S;
>
> ...here we're setting the wrong dword. This should be
>
>         cmd->dword1 = FIELD_PREP(RISCV_IOMMU_CMD_IOTINVAL_ADDR, pfn) |
>                       RISCV_IOMMU_CMD_IOTINVAL_S;
>         cmd->dword0 |= RISCV_IOMMU_CMD_IOTINVAL_AV;
>
> Thanks,
> drew

Yes, good catch. Similar to the RFC commit [1] ...

- Tomasz

[1] https://github.com/tjeznach/linux/commit/ef51d4be750d2d7c449747ab53fd5c12d5a4a175