[PATCH v3 0/3] microchip core-qspi gpio-cs fixes + cleanup

Mark Brown broonie at kernel.org
Mon May 4 06:23:08 PDT 2026


On Thu, 30 Apr 2026 11:10:17 +0100, Conor Dooley wrote:
> microchip core-qspi gpio-cs fixes + cleanup
> 
> From: Conor Dooley <conor.dooley at microchip.com>
> 
> Hey Mark,
> 
> v3 with the review comment about the core handing CS_HIGH dealt with.
> I noticed that in the same function there was a "raw" BIT(1), which I
> replaced with a macro that the patch was already adding for use in the
> setup function...
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-7.1

Thanks!

[1/3] spi: microchip-core-qspi: control built-in cs manually
      https://git.kernel.org/broonie/spi/c/7672749e1496
[2/3] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations
      https://git.kernel.org/broonie/spi/c/eb56deaabf12
[3/3] spi: microchip-core-qspi: remove some inline markings
      https://git.kernel.org/broonie/spi/c/0b2eb1f8473e

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark




More information about the linux-riscv mailing list