[PATCH RFC] riscv: disable local interrupts and stop other CPUs before restart

Anand Moon linux.amoon at gmail.com
Mon May 4 06:27:26 PDT 2026


Hi Aurelien

On Sun, 26 Apr 2026 at 17:51, Aurelien Jarno <aurelien at aurel32.net> wrote:
>
> Hi Anand,
>
> On 2026-04-25 23:12, Anand Moon wrote:
> > Hi All,
> >
> > On Fri, 24 Apr 2026 at 02:21, Aurelien Jarno <aurelien at aurel32.net> wrote:
> > >
> > > Hi,
> > >
> > > On 2026-03-16 08:19, Samuel Holland wrote:
> > > > Hi Troy,
> > > >
> > > > On 2026-03-16 2:23 AM, Troy Mitchell wrote:
> > > > >> I think the reason we ended up with the "unsafe" implementations of the
> > > > >> reboot/shutdown functions is that on the backend it is usually SBI SRST
> > > > >> calls, which can protect itself from other CPUs and interrupts. Since on
> > > > >> K1 we're going to be poking I2C directly, we run into the problem
> > > > >> described above. So all of these should disable interrupts and stop
> > > > >> other CPUs before calling the handlers, and can't assume the handlers
> > > > >> are all SBI SRST.
> > > > > Yes, we cannot assume that all platforms rely on this.
> > > >
> > > > Why isn't K1 using the SBI SRST extension? Resetting the platform from S-mode
> > > > directly causes problems if you ever want to run another supervisor domain (for
> > > > example a TEE or EFI runtime services), which may need to clean up before a
> > > > system reset.
> > > >
> > > > As you mention, other platforms use the standard SBI SRST interface, event if
> > > > they need to poke a PMIC to perform a system reset. Is there something
> > > > preventing K1 from following this path?
> > >
> > > I went this path and submitted a patchset to OpenSBI mailing list doing
> > > that:
> > > https://lore.kernel.org/opensbi/20260419150857.2705843-1-aurelien@aurel32.net/T/#t
> > >
> > I just wanted to check if we can use the latest OpenSBI image with
> > vendor u-boot ?
> > If so, can you share the details of flash the u-boot and OpenSBI binaries? .
>
> That is a good question, and no this doesn't work out of the box.
>
> > I was working on the watchdog driver, and the system hangs at reboot
> > So, what changes do we need to make in OpenSBI to handle this issue?
>
> This can be addressed either by making OpenSBI compatible with the
> vendor U-Boot, or by making the vendor U-Boot compatible with the
> upstream OpenSBI. On my side, I prefer the latter option as it also
> keeps the upstream OpenSBI compatible with the (future) upstream U-Boot.
>
> I have just published a blog post about how to do that:
> https://blog.aurel32.net/upstream-opensbi-spacemit-k1.html
>
I’ve completed the build — the Yocto image compiled successfully from
your Git repository.

U-Boot SPL 2022.10spacemit-gc6f2746c (Aug 20 2025 - 14:53:37 +0000)
[   0.371] DDR type LPDDR4X
[   0.371] set ddr tx odt to 80ohm!
[   0.386] lpddr4_silicon_init consume 15ms
[   0.387] Change DDR data rate to 2400MT/s
[   2.172] ## Checking hash(es) for config conf-1 ... OK
[   2.174] ## Checking hash(es) for Image opensbi ... OK
[   2.179] ## Checking hash(es) for Image uboot ... OK
[   2.184] ## Checking hash(es) for Image fdt-1 ... OK
[   2.189] ## Checking hash(es) for Image kernel-1 ... OK
[   2.205] ## Checking hash(es) for Image fdt-2 ... OK
mmc_load_image_raw_sector: mmc block read error

OpenSBI v1.8.1
   ____                    _____ ____ _____
  / __ \                  / ____|  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |____) | |_) || |_
  \____/| .__/ \___|_| |_|_____/|____/_____|
        | |
        |_|

Platform Name               : Banana Pi BPI-F3
Platform Features           : medeleg
Platform HART Count         : 8
Platform HART Protection    : pmp
Platform IPI Device         : aclint-mswi
Platform Timer Device       : aclint-mtimer @ 24000000Hz
Platform Console Device     : uart8250
Platform HSM Device         : spacemit-hsm
Platform PMU Device         : ---
Platform Reboot Device      : ---
Platform Shutdown Device    : ---
Platform Suspend Device     : ---
Platform CPPC Device        : ---
Firmware Base               : 0x0
Firmware Size               : 407 KB
Firmware RW Offset          : 0x40000
Firmware RW Size            : 151 KB
Firmware Heap Offset        : 0x55000
Firmware Heap Size          : 67 KB (total), 1 KB (reserved), 13 KB
(used), 52 KB (free)
Firmware Scratch Size       : 4096 B (total), 1464 B (used), 2632 B (free)
Runtime SBI Version         : 3.0
Standard SBI Extensions     :
time,rfnc,ipi,base,hsm,pmu,dbcn,fwft,legacy,dbtr,sse
Experimental SBI Extensions : none

Since I don't have your opensbi patch in my email.
Please feel free to add
Tested-by: Anand Moon <linux.amoon at gmail.com>

 > Regards
> Aurelien
>
> --
> Aurelien Jarno                          GPG: 4096R/1DDD8C9B
> aurelien at aurel32.net                     http://aurel32.net

Thanks
-Anand



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