[PATCH 3/7] dt-bindings: riscv: cpus: Add Tenstorrent Ascalon

[Conor Dooley]

On Wed, Jun 03, 2026 at 05:12:15PM +0930, Joel Stanley wrote:
> Add Tenstorrent Ascalon microarchitecture and the Tenstorrent Ascalon-XG
> core.
> 
> Signed-off-by: Drew Fustini <fustini at kernel.org>
> Signed-off-by: Joel Stanley <joel at jms.id.au>

Same here.
pw-bot: changes-requested

> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 5feeb2203050..2a57bd14569e 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -75,6 +75,11 @@ properties:
>                - sifive,x280
>            - const: sifive,rocket0
>            - const: riscv
> +      - items:
> +          - enum:
> +              - tenstorrent,ascalon-xg
> +          - const: tenstorrent,ascalon
> +          - const: riscv
>        - const: riscv    # Simulator only
>      description:
>        Identifies that the hart uses the RISC-V instruction set
> -- 
> 2.47.3
> 
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