[PATCH v10 2/3] clk: canaan: Add clock driver for Canaan K230

[Xukai Wang]

On 2026/1/19 16:18, Jiayu Du wrote:
>> +
>> +K230_CLK_GATE_FORMAT(hs_hclk_src_gate,
>> +		     K230_HS_HCLK_SRC_GATE,
>> +		     0x18, 0, 0, 0,
>> +		     &hs_hclk_high_src_rate.clk.hw);
> Here, you replaced hs_hclk_high_gate(in v9) with hs_hclk_high_src_rate,

I'm a bit confused, as I don't recall making these specific changes.
Looking at the code below, the only difference between v9 and v10 is
within the K230_CLK_GATE_FORMAT(hs_hclk_src_gate, ...) definition, where
the second parameter changed from 1 to 0. Everything else appears
consistent. Could you clarify which change you were referring to?

The code

in v8:

+K230_CLK_RATE_FORMAT(hs_hclk_high_src_rate, +
K230_HS_HCLK_HIGH_SRC_RATE, + 1, 1, 0, 0, + 1, 8, 0, 0x7, + 0x1C, 31,
div, 0x0, + false, 0, + &pll0_div4.hw); +
+K230_CLK_GATE_FORMAT(hs_hclk_high_gate, + K230_HS_HCLK_HIGH_GATE, +
0x18, 1, 0, 0, + &hs_hclk_high_src_rate.clk.hw); +
+K230_CLK_GATE_FORMAT(hs_hclk_src_gate, + K230_HS_HCLK_SRC_GATE, + 0x18,
1, 0, 0, + &hs_hclk_high_src_rate.clk.hw); +
+K230_CLK_RATE_FORMAT(hs_hclk_src_rate, + K230_HS_HCLK_SRC_RATE, + 1, 1,
0, 0, + 1, 8, 3, 0x7, + 0x1C, 31, div, 0x0, + false, 0, +
&hs_hclk_src_gate.clk.hw);

in v9:

+K230_CLK_RATE_FORMAT(hs_hclk_high_src_rate, +
K230_HS_HCLK_HIGH_SRC_RATE, + 1, 1, 0, 0, + 1, 8, 0, 0x7, + 0x1C, 31,
div, 0x0, + false, 0, + &pll0_div4.hw); +
+K230_CLK_GATE_FORMAT(hs_hclk_high_gate, + K230_HS_HCLK_HIGH_GATE, +
0x18, 1, 0, 0, + &hs_hclk_high_src_rate.clk.hw); +
+K230_CLK_GATE_FORMAT(hs_hclk_src_gate, + K230_HS_HCLK_SRC_GATE, + 0x18,
1, 0, 0, + &hs_hclk_high_src_rate.clk.hw); +
+K230_CLK_RATE_FORMAT(hs_hclk_src_rate, + K230_HS_HCLK_SRC_RATE, + 1, 1,
0, 0, + 1, 8, 3, 0x7, + 0x1C, 31, div, 0x0, + false, 0, +
&hs_hclk_src_gate.clk.hw); +

in v10:

+K230_CLK_RATE_FORMAT(hs_hclk_high_src_rate, +
K230_HS_HCLK_HIGH_SRC_RATE, + 1, 1, 0, 0, + 1, 8, 0, 0x7, + 0x1C, 31,
div, 0x0, + false, 0, + &pll0_div4.hw); +
+K230_CLK_GATE_FORMAT(hs_hclk_high_gate, + K230_HS_HCLK_HIGH_GATE, +
0x18, 1, 0, 0, + &hs_hclk_high_src_rate.clk.hw); +
+K230_CLK_GATE_FORMAT(hs_hclk_src_gate, + K230_HS_HCLK_SRC_GATE, + 0x18,
0, 0, 0, + &hs_hclk_high_src_rate.clk.hw); +
+K230_CLK_RATE_FORMAT(hs_hclk_src_rate, + K230_HS_HCLK_SRC_RATE, + 1, 1,
0, 0, + 1, 8, 3, 0x7, + 0x1C, 31, div, 0x0, + false, 0, +
&hs_hclk_src_gate.clk.hw);

> but after my board test, I find that when hs_hclk_high_gate is turned
> off, the mmc/sd and other high-speed subsystems can not work. So maybe
> you should not change the hs_hclk_high_gate to hs_hclk_high_src_rate.

Regarding the clock management, I recommend explicitly enabling
hs_hclk_high_gateas it will be closed by `close unused clocks`.

>
> When I used clk_ignore_unused, I saw the log as follows, while the enable
> and prepare count of hs_hclk_high_gate is zero. Here is the log:
>        pll0_div4                     5  5  0  400000000   0   0     50000      Y  deviceless   no_connection_id
>           hs_hclk_high_src_rate      1  1  0  400000000   0   0     50000      Y     deviceless   no_connection_id
>              hs_hclk_high_gate       0  0  0  400000000   0   0     50000      Y        deviceless   no_connection_id
>              hs_hclk_src_gate        1  1  0  400000000   0   0     50000      Y        deviceless   no_connection_id
>                 hs_hclk_src_rate     4  4  0  200000000   0   0     50000      Y           deviceless   no_connection_id
>                    hs_sd0_ahb_gate   1  1  0  200000000   0   0     50000      Y              91580000.mmc   ahb
>                                                                                             deviceless   no_connection_id
>                    hs_sd1_ahb_gate   1  1  0  200000000   0   0     50000      Y              91581000.mmc   ahb
>                                                                                             deviceless   no_connection_id
>                    hs_ssi1_ahb_gate  0  0  0  200000000   0   0     50000      Y              deviceless   no_connection_id
>                    hs_ssi2_ahb_gate  0  0  0  200000000   0   0     50000      Y              deviceless   no_connection_id
>                    hs_usb0_ahb_gate  1  1  0  200000000   0   0     50000      Y              91500000.usb   otg
>                                                                                             deviceless   no_connection_id
>                    hs_usb1_ahb_gate  1  1  0  200000000   0   0     50000      Y              91540000.usb   otg
>
> Regards,
> Jiayu Du
>> +
>> +K230_CLK_RATE_FORMAT(hs_hclk_src_rate,
>> +		     K230_HS_HCLK_SRC_RATE,