[PATCH v10 2/3] clk: canaan: Add clock driver for Canaan K230
Jiayu Du
jiayu.riscv at isrc.iscas.ac.cn
Mon Jan 19 00:18:59 PST 2026
> +
> +K230_CLK_GATE_FORMAT(hs_hclk_src_gate,
> + K230_HS_HCLK_SRC_GATE,
> + 0x18, 0, 0, 0,
> + &hs_hclk_high_src_rate.clk.hw);
Here, you replaced hs_hclk_high_gate(in v9) with hs_hclk_high_src_rate,
but after my board test, I find that when hs_hclk_high_gate is turned
off, the mmc/sd and other high-speed subsystems can not work. So maybe
you should not change the hs_hclk_high_gate to hs_hclk_high_src_rate.
When I used clk_ignore_unused, I saw the log as follows, while the enable
and prepare count of hs_hclk_high_gate is zero. Here is the log:
pll0_div4 5 5 0 400000000 0 0 50000 Y deviceless no_connection_id
hs_hclk_high_src_rate 1 1 0 400000000 0 0 50000 Y deviceless no_connection_id
hs_hclk_high_gate 0 0 0 400000000 0 0 50000 Y deviceless no_connection_id
hs_hclk_src_gate 1 1 0 400000000 0 0 50000 Y deviceless no_connection_id
hs_hclk_src_rate 4 4 0 200000000 0 0 50000 Y deviceless no_connection_id
hs_sd0_ahb_gate 1 1 0 200000000 0 0 50000 Y 91580000.mmc ahb
deviceless no_connection_id
hs_sd1_ahb_gate 1 1 0 200000000 0 0 50000 Y 91581000.mmc ahb
deviceless no_connection_id
hs_ssi1_ahb_gate 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id
hs_ssi2_ahb_gate 0 0 0 200000000 0 0 50000 Y deviceless no_connection_id
hs_usb0_ahb_gate 1 1 0 200000000 0 0 50000 Y 91500000.usb otg
deviceless no_connection_id
hs_usb1_ahb_gate 1 1 0 200000000 0 0 50000 Y 91540000.usb otg
Regards,
Jiayu Du
> +
> +K230_CLK_RATE_FORMAT(hs_hclk_src_rate,
> + K230_HS_HCLK_SRC_RATE,
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