[PATCH v1 00/20] Add basic pinctrl drivers for JHB100 SoC

[Linus Walleij]

Hi Changhuang,

thanks for your patch!

On Fri, Apr 24, 2026 at 1:13 PM Changhuang Liang
<changhuang.liang at starfivetech.com> wrote:

> The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,
> per2, per2pok, per3, adc0, adc1, emmc, and vga.
>
> In the current series, we will only add the following pinctrl:
>  - sys0, sys0h, sys1, sys2
>  - per0, per1, per2, per2pok, per3
>
> The remaining pinctrl will be implemented in future series.
>
> This series depends on the series:
> https://lore.kernel.org/all/20260402105523.447523-1-changhuang.liang@starfivetech.com/

(...)

>  .../starfive/pinctrl-starfive-jhb100.c        | 1821 +++++++++++++++++

Thats a big patch.

I need a motivation why the existing code in pinctrl-starfive-jh7110.c
and pinctrl-starfive-jh7100.c cannot be refactored, repurposed and
re-used of this hardware is related to the old hardware?

We don't want several copies of essentially the same driver, that
way we get maintenance overload.

So the first question about this patch set is if a completely new
driver is really needed.

A second question regards "banks" in the GPIO controller.
The callbacks offsets are exensively /32 %32 MOD:ed to clamp
to 32bit words. Should this rather be reflected in the device
tree model as a 3-cell GPIO <&gpio bank num flags> rather
than 2-cell <&gpio num flags>? Doing this makes it possible
to use gpiolib helpers.

Yours,
Linus Walleij