[PATCH v2 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache

[Conor Dooley]

On Sat, May 03, 2025 at 11:18:26PM +0800, Ben Zong-You Xie wrote:
> The current device tree binding for the Andes AX45MP L2 cache enforces
> a fixed number of cache-sets (1024). However, there are 2048 cache-sets in
> the QiLai SoC. This change allows both 1024 and 2048 as valid values for
> "cache-sets".
> 
> Signed-off-by: Ben Zong-You Xie <ben717 at andestech.com>
> Acked-by: Rob Herring (Arm) <robh at kernel.org>

Applied, thanks.
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