[PATCH v5 3/5] clk: spacemit: Add clock support for Spacemit K1 SoC

[kernel test robot]

Hi Haylen,

kernel test robot noticed the following build warnings:

[auto build test WARNING on spacemit/for-next]
[also build test WARNING on spacemit/fixes clk/clk-next robh/for-next linus/master v6.14-rc6 next-20250312]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Haylen-Chu/dt-bindings-soc-spacemit-Add-spacemit-k1-syscon/20250307-020635
base:   https://github.com/spacemit-com/linux for-next
patch link:    https://lore.kernel.org/r/20250306175750.22480-5-heylenay%404d2.org
patch subject: [PATCH v5 3/5] clk: spacemit: Add clock support for Spacemit K1 SoC
config: powerpc64-randconfig-r131-20250312 (https://download.01.org/0day-ci/archive/20250313/202503130314.Y8KFKZWW-lkp@intel.com/config)
compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff)
reproduce: (https://download.01.org/0day-ci/archive/20250313/202503130314.Y8KFKZWW-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503130314.Y8KFKZWW-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/clk/spacemit/ccu_pll.c:110:9: sparse: sparse: cast truncates bits from constant value (ffffffff7fffffff becomes 7fffffff)

vim +110 drivers/clk/spacemit/ccu_pll.c

    85	
    86	/*
    87	 * PLLs must be gated before changing rate, which is ensured by
    88	 * flag CLK_SET_RATE_GATE.
    89	 */
    90	static int ccu_pll_set_rate(struct clk_hw *hw, unsigned long rate,
    91				    unsigned long parent_rate)
    92	{
    93		struct ccu_pll *p = hw_to_ccu_pll(hw);
    94		struct ccu_common *common = &p->common;
    95		struct ccu_pll_config *params = &p->pll;
    96		const struct ccu_pll_rate_tbl *entry = NULL;
    97		int i;
    98	
    99		for (i = 0; i < params->tbl_size; i++) {
   100			if (rate == params->rate_tbl[i].rate) {
   101				entry = &params->rate_tbl[i];
   102				break;
   103			}
   104		}
   105	
   106		if (WARN_ON_ONCE(!entry))
   107			return -EINVAL;
   108	
   109		ccu_update(swcr1, common, entry->swcr1, entry->swcr1);
 > 110		ccu_update(swcr3, common, (u32)~PLL_SWCR3_EN, entry->swcr3);
   111	
   112		return 0;
   113	}
   114	

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