[PATCH 7/8] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC

[Guodong Xu]

On Tue, Dec 16, 2025 at 11:35 PM Krzysztof Kozlowski <krzk at kernel.org> wrote:
>
> On 16/12/2025 14:32, Guodong Xu wrote:
> > SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant.
> > Add nodes of uarts, timer and interrupt-controllers.
> >
> > Signed-off-by: Guodong Xu <guodong at riscstar.com>
> > ---
> >  arch/riscv/boot/dts/spacemit/k3.dtsi | 529 +++++++++++++++++++++++++++++++++++
> >  1 file changed, 529 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..cb27b790716fdd6dc2bc89c28dd2588a596a5af9
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
> > @@ -0,0 +1,529 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (c) 2025 SpacemiT (Hangzhou) Technology Co. Ltd
> > + * Copyright (c) 2025 Guodong Xu <guodong at riscstar.com>
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/dts-v1/;
> > +
> > +/ {
> > +     #address-cells = <2>;
> > +     #size-cells = <2>;
> > +     model = "SpacemiT K3";
> > +     compatible = "spacemit,k3";
> > +
> > +     aliases {
> > +             serial0 = &uart0;
> > +             serial2 = &uart2;
> > +             serial3 = &uart3;
> > +             serial4 = &uart4;
> > +             serial5 = &uart5;
> > +             serial6 = &uart6;
> > +             serial7 = &uart7;
> > +             serial8 = &uart8;
> > +             serial9 = &uart9;
> > +             serial10 = &uart10;
>
> These are not properties of the soc, but the board DTS.

Thank you Krzysztof, I will fix that in the next version.

Best regards,
Guodong Xu

>
> Best regards,
> Krzysztof