[PATCH v3 00/22] riscv: Memory type control for platforms with physical memory aliases

[Nick Kossifidis]

On 11/13/25 03:45, Samuel Holland wrote:
> 
> On some RISC-V platforms, including StarFive JH7100 and ESWIN EIC7700,
> DRAM is mapped to multiple physical address ranges, with each alias
> having a different set of statically-determined Physical Memory
> Attributes (PMAs), such as cacheability. Software can alter the PMAs for
> a page by selecting a PFN from the corresponding physical address range.
> On these platforms, this is the only way to allocate noncached memory
> for use with noncoherent DMA.
> 
Then why don't you solve this at the DMA API layer ? Are those 
alternative PMAs going to be used for something else ? If the only 
usecase is to support noncoherent DMA I suggest playing with 
arch_dma_set_uncached and/or arch_dma_prep_coherent, we can deal with 
this similar to how MIPS did it with UNCAC_BASE.

Regards,
Nick