[PATCH 7/9] riscv: dts: andes: add QiLai SoC device tree

[Krzysztof Kozlowski]

On 07/04/2025 12:49, Ben Zong-You Xie wrote:
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;

This belongs to the board.

> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <62500000>;
> +
> +		cpu0: cpu at 0 {
> +			compatible = "andestech,ax45mp", "riscv";
> +			device_type = "cpu";
> +			status = "okay";

Drop. See DTS coding style.


...

> +
> +	memory at 400000000 {
> +		device_type = "memory";
> +		reg = <0x4 0x00000000 0x4 0x00000000>;

This belongs to the board usually. Are you sure your SoC has physically
fixed memory?

> +	};
> +
> +	soc {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		compatible = "simple-bus";
> +		ranges;
> +
> +		plic: interrupt-controller at 2000000 {
> +			compatible = "andestech,qilai-plic", "andestech,nceplic100";
> +			#address-cells = <0>;
> +			#interrupt-cells = <2>;
> +			interrupt-controller;
> +			reg = <0x0 0x2000000 0x0 0x2000000>;
> +			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> +					      <&cpu1_intc 11>, <&cpu1_intc 9>,
> +					      <&cpu2_intc 11>, <&cpu2_intc 9>,
> +					      <&cpu3_intc 11>, <&cpu3_intc 9>;
> +			riscv,ndev = <71>;
> +		};
> +
> +		plic_sw: interrupt-controller at 400000 {
> +			compatible = "andestech,qilai-plicsw", "andestech,plicsw";
> +			reg = <0x0 0x400000 0x0 0x400000>;
> +			interrupts-extended = <&cpu0_intc 3>,
> +					      <&cpu1_intc 3>,
> +					      <&cpu2_intc 3>,
> +					      <&cpu3_intc 3>;
> +		};
> +
> +		plmt: timer at 100000 {

Order the nodes, see DTS coding style.


Best regards,
Krzysztof