[PATCH 7/9] riscv: dts: andes: add QiLai SoC device tree
Ben Zong-You Xie
ben717 at andestech.com
Mon Apr 7 03:49:35 PDT 2025
Introduce the initial device tree support for the Andes QiLai SoC.
For further information, you can refer to [1].
[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
Signed-off-by: Ben Zong-You Xie <ben717 at andestech.com>
---
MAINTAINERS | 1 +
arch/riscv/boot/dts/andes/qilai.dtsi | 194 +++++++++++++++++++++++++++
2 files changed, 195 insertions(+)
create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index d1e1b98dfe7b..b974e83c9f10 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20731,6 +20731,7 @@ S: Maintained
F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw.yaml
F: Documentation/devicetree/bindings/riscv/andes.yaml
F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml
+F: arch/riscv/boot/dts/andes/
RISC-V ARCHITECTURE
M: Paul Walmsley <paul.walmsley at sifive.com>
diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
new file mode 100644
index 000000000000..7199a88afc9b
--- /dev/null
+++ b/arch/riscv/boot/dts/andes/qilai.dtsi
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = <62500000>;
+
+ cpu0: cpu at 0 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ status = "okay";
+ reg = <0>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "zicntr", "zicsr", "zifencei",
+ "zihpm", "xandespmu";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <100000000>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-line-size = <64>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <128>;
+ d-cache-line-size = <64>;
+ next-level-cache = <&l2_cache>;
+
+ cpu0_intc: interrupt-controller {
+ compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu1: cpu at 1 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ status = "okay";
+ reg = <1>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "zicntr", "zicsr", "zifencei",
+ "zihpm", "xandespmu";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <100000000>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-line-size = <64>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <128>;
+ d-cache-line-size = <64>;
+ next-level-cache = <&l2_cache>;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu2: cpu at 2 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ status = "okay";
+ reg = <2>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "zicntr", "zicsr", "zifencei",
+ "zihpm", "xandespmu";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <100000000>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-line-size = <64>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <128>;
+ d-cache-line-size = <64>;
+ next-level-cache = <&l2_cache>;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ cpu3: cpu at 3 {
+ compatible = "andestech,ax45mp", "riscv";
+ device_type = "cpu";
+ status = "okay";
+ reg = <3>;
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "zicntr", "zicsr", "zifencei",
+ "zihpm", "xandespmu";
+ mmu-type = "riscv,sv39";
+ clock-frequency = <100000000>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <256>;
+ i-cache-line-size = <64>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <128>;
+ d-cache-line-size = <64>;
+ next-level-cache = <&l2_cache>;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "andestech,cpu-intc", "riscv,cpu-intc";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+ };
+
+ memory at 400000000 {
+ device_type = "memory";
+ reg = <0x4 0x00000000 0x4 0x00000000>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ plic: interrupt-controller at 2000000 {
+ compatible = "andestech,qilai-plic", "andestech,nceplic100";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0x0 0x2000000 0x0 0x2000000>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>;
+ riscv,ndev = <71>;
+ };
+
+ plic_sw: interrupt-controller at 400000 {
+ compatible = "andestech,qilai-plicsw", "andestech,plicsw";
+ reg = <0x0 0x400000 0x0 0x400000>;
+ interrupts-extended = <&cpu0_intc 3>,
+ <&cpu1_intc 3>,
+ <&cpu2_intc 3>,
+ <&cpu3_intc 3>;
+ };
+
+ plmt: timer at 100000 {
+ compatible = "andestech,qilai-aclint-mtimer", "andestech,plmt0";
+ reg = <0x0 0x100000 0x0 0x100000>;
+ interrupts-extended = <&cpu0_intc 7>,
+ <&cpu1_intc 7>,
+ <&cpu2_intc 7>,
+ <&cpu3_intc 7>;
+ };
+
+ l2_cache: cache-controller at 200000 {
+ compatible = "andestech,ax45mp-cache", "cache";
+ reg = <0x0 0x200000 0x0 0x100000>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&plic>;
+ cache-line-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <0x200000>;
+ cache-unified;
+ };
+
+ uart0: serial at 30300000 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0x0 0x30300000 0x0 0x100000>;
+ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <50000000>;
+ reg-offset = <32>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ no-loopback-test;
+ interrupt-parent = <&plic>;
+ };
+ };
+};
--
2.34.1
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