[PATCH v11 2/5] dt-bindings: clock: sophgo: add RP gate clocks for SG2042

[Chen Wang]

On 2024/3/9 10:15, Stephen Boyd wrote:
> Quoting Chen Wang (2024-02-19 19:08:59)
>> +required:
>> +  - compatible
>> +  - reg
>> +  - clocks
>> +  - '#clock-cells'
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    clock-controller at 10000000 {
> This is the same address as the pll binding before this. How does that
> work? It's the same register area as the pll node. The resulting DTB
> should only have one compatible for this node.

Hi, Stephen,

This is just examples in bindings file, it should be no problem. The 
resulting DTS/DTB will have different addresses.

And I see you mentined you have alreay applied this binding to clk-next 
in another email. right?

Thanks,

Chen

>
>> +      compatible = "sophgo,sg2042-rpgate";
>> +      reg = <0x10000000 0x10000>;
>> +      clocks = <&clkgen 85>;
>> +      #clock-cells = <1>;
>> +    };